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Overview

The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present. Highspeed data transmission is enabled by the 4 lane PCIe Gen 2 interface.

The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD.

The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host system to meet the power supply requirements.

Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation.

Key Features

• Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC
• Large number of configurable I/Os are provided via HPC FMC connector
  • 4 GTX high-performance transceiver
  • 2x MGT transceiver clock inputs
  • 160 FPGA I/O's (80 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• Lattice MachXO2 LCMXO2-1200HC System Controller CPLD
• 10x User LEDs
• PCI Express x8 connector with 4 lane PCIe Gen 2 interface
• ANSI Vita 57.1 FMC High Pin Count (HPC) connector
• DDR3 SODIMM SDRAM with ECC socket with 64bit databus width
• 256Mbit (32MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect, bus width x4)
• FPGA configuration through:
  • JTAG connector
  • Quad SPI Flash memory

• Clocking

  • Si5338 programmable quad PLL clock generator - 4 outputs for MGT and PL clocks

  • 200MHz oscillator for DDR3 bank

• System management and power sequencing
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

1. Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
2. ANSI/VITA 57.1 compliant FMC HPC connector, J2
3. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
4. PCIe x8 connector, J1
5. DDR3 SODIMM 204-pin socket, U2
6. 6-pin 12V power connector, J5
7. Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
8. Step-down DC-DC converter @1.0V (LT LTM4676A), U4
9. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
10. 10x Green user LEDs connected to FPGA, D1 ... D10
11. 4-wire PWM fan connector, J4
12. User button, S2
13. FPGA JTAG connector, J9
14. 4bit DIP switch, S1
15. I²C header for LTM4676A DC-DC converter, J10
16. System Controller CPLD JTAG header, J8
17. 1x Green LED connected to SC CPLD, D11
18. 2-pin 5V FAN header, J6
19. System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
20. 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
21. 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
22. LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
23. LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
24. 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7

Initial Delivery State

Control Signals

To get started with TEF1001 board, some basic control signals are essential and are described in the following table:

Signals, Interfaces and Pins

FMC HPC Connector

I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J2:

For detailed information about the pin out, please refer to the Pin-out Tables.

FMC connector J2 MGT Lanes:

FMC connector J2 reference clock sources:

FMC connector J2 VCC/VCCIO:

FMC connector J2 Cooling Fan:

PCI Express Interface

The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots and has a data transmission capability which meets PCIe Gen. 2 with 4 GTX lanes routed to the PCIe interface.

Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

JTAG Connectors

There are two JTAG connectors J8 and J9 available on the TEF1001 board:

FAN Connectors

The TEF1001 board offers one FAN connector for cooling the FPGA device and one built-in FAN for the FMC modules.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U5) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the board's SC CPLD or into its bitstream file.. Table below lists the SC CPLD I/O pins with their default configuration:

DDR3 SDRAM ECC SO-DIMM Socket

The TEF1001 board supports additional DDR3 ECC SO-DIMM via 204-pin socket U2. The DDR3 memory interface has a 64bit wide databus and is routed to the FPGA banks 32, 33 and 34.

The reference clock signal for the DDR3 interface is generated by the 200.0000MHz MEMS oscillator U1 and is applied to the FPGA bank 33.

There is also a I²C interface between the System Controller CPLD U5 and the DDR3 ECC SO-DIMM memory socket U2.

Quad SPI Flash Memory

A 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Quad SPI Flash memory interface is connected to the FPGA bank 14, QSPI clock is provided by FPGA config bank 0.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U13) to generate various reference clocks for the module.

Oscillators

The FPGA module has following reference clocking sources provided by on-board oscillators and FMC connector J2:

On-board LEDs

Configuration DIP-switch

There is one 4-bit DIP-witches S1 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:

Push Buttons

There is one push buttons available to the user connected to the SC CPLD U5:

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

 * TBD - To Be Determined soon with reference design setup.

It is recommended to connect the ATX connector J5 to a 12V power supply source with minimum current capability of 6A to provide a sufficient power source to the board. Only one power source is needed at the same time, the system disconnects automatically PCIe power supply from PCIe edge connector J1 if the board is powered by the ATX connector J5.

Power Distribution Dependencies

Power-On Sequence

The TEF1001 board meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.
Some of the voltages are handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Bank Voltages

Power Rails

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

1) Temperature range may vary depending on assembly options

2) The operating temperature range of the FPGA soC and on-board peripherals are junction and also ambient operating temperature ranges

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Variants Currently In Production

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Date Revision Authors Description update picture 2018-10-24 v.41 Guillermo Herrera Initial document

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