Template Revision 2.3
TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
  width: 100% !important;
  max-width: 1200px !important;

Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment

    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


Note for Download Link of the Scroll ignore macro:

Download PDF version of this document.

Table of Contents


Notes :

The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present. Highspeed data transmission is enabled by the 4 lane PCIe Gen 2 interface.

The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD.

The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host system to meet the power supply requirements.

Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation.

Key Features


  • List of key features of the PCB

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

  1. Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
  2. ANSI/VITA 57.1 compliant FMC HPC connector, J2
  3. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
  4. PCIe x8 connector, J1
  5. DDR3 SODIMM 204-pin socket, U2
  6. 6-pin 12V power connector, J5
  7. Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
  8. Step-down DC-DC converter @1.0V (LT LTM4676A), U4
  9. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
  10. 10x Green user LEDs connected to FPGA, D1 ... D10
  11. 4-wire PWM fan connector, J4
  12. User button, S2
  13. FPGA JTAG connector, J9
  14. 4bit DIP switch, S1
  15. I²C header for LTM4676A DC-DC converter, J10
  16. System Controller CPLD JTAG header, J8
  17. 1x Green LED connected to SC CPLD, D11
  18. 2-pin 5V FAN header, J6
  19. System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
  20. 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
  21. 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
  22. LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
  23. LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
  24. 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7

Initial Delivery State

Storage device nameContentNotes
Si5338A OTP Areanot programmed-

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit



SPI Flash main array

demo design

HyperFlash Memorynot programmed-


Not programmed


eFUSE Security

Not programmed


Control Signals

To get started with TEF1001 board, some basic control signals are essential and are described in the following table:

Control signal

Switch / Button / LED / PinSignal Schematic Names

Connected to


SC CPLD JTAG EnableDIP switch S1-1JTAG_ENSC CPLD U5, pin 82

ON-position: SC CPLD U5 JTAG interface enabled

BOOT ModeFPGA bank 0, pins T5, T2, P5-

Pin T5 (M0): 1V8
Pin T2 (M1): GND
Pin P5 (M2): GND

Hard-wired Boot ModeBy default the configuration mode pins M[2:0] of the
FPGA are set to QSPI mode (Master SPI)
Global Reset inputPush Button S2S2SC CPLD U5, pin 77Manual reset from user-
FMC_VADJ voltage selectionDIP switches S1-2, S1-3, S1-4VID0_FMC_VADJ_CTRL ...
SC CPLD U5, pins 71, 63, 62sets adjustable voltage 'FMC_VADJ' for FMC connectorDIP-switch states forwarded by SC CPLD U5
to DC-DC U7. Refer to section Configuration
DIP-switch for more details.

Signals, Interfaces and Pins


  • For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

FMC HPC Connector

I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J2:

InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O4824FPGA Bank 12 HRFMC_VADJBank voltage FMC_VADJ is supplied by DC-DC converter U7
4444FPGA Bank 16 HRVIO_B_FMCBank voltage VIO_B_FMC is supplied by FMC connector J2
I²C2-SC CPLD U5, Bank 2, pin 48, 49-FMC connector J2 is hardware programmed to I²C address 0x50
JTAG5-SC CPLD U5, Bank 2, pin 27, 28, 331, 32 ,363.3V4 JTAG pins with additional signal 'TRST'
MGT-8 (4 x RX/TX)Bank 116 GTX-4x MGT lanes
Clock Input-2Bank 116 GTX-2x Reference clock input to MGT bank
Control Signals3-SC CPLD U5, Bank 1, pin 68, 69 ,703.3V


For detailed information about the pin out, please refer to the Pin-out Tables.

FMC connector J2 MGT Lanes:

MGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin
  • DP3_M2C_P
  • DP3_M2C_N
  • DP3_C2M_P
  • DP3_C2M_N
  • J2-A10
  • J2-A11
  • J2-A30
  • J2-A31
  • MGTXRXP0_116, G4
  • MGTXRXN0_116, G3
  • MGTXTXP0_116, F2
  • MGTXTXN0_116, F1
  • DP2_M2C_P
  • DP2_M2C_N
  • DP2_C2M_P
  • DP2_C2M_N
  • J2-A6
  • J2-A7
  • J2-A26
  • J2-A27
  • MGTXRXP1_116, E4
  • MGTXRXN1_116, E3
  • MGTXTXP1_116, D2
  • MGTXTXN1_116, D1
  • DP1_M2C_P
  • DP1_M2C_N
  • DP1_C2M_P
  • DP1_C2M_N
  • J2-A2
  • J2-A3
  • J2-A22
  • J2-A23
  • MGTXRXP2_116, C4
  • MGTXRXN2_116, C3
  • MGTXTXP2_116, B2
  • MGTXTXN2_116, B1
  • DP0_M2C_P
  • DP0_M2C_N
  • DP0_C2M_P
  • DP0_C2M_N
  • J2-C6
  • J2-C7
  • J2-C2
  • J2-C3
  • MGTXRXP3_116, B6
  • MGTXRXN3_116, B5
  • MGTXTXP3_116, A4
  • MGTXTXN3_116, A3

FMC connector J2 reference clock sources:

Signal Schematic NameConnected toFMC Connector PinFPGA PinNotes
MGT bank 116



Supplied by attached FMC module
MGT bank 116J2-B20
Supplied by attached FMC module

FMC connector J2 VCC/VCCIO:

Available VCC/VCCIOFMC Connector PinSourceNotes


max. current: 4A

Enable by SC CPLD U5, bank 1, pin 60
Signal: 'EN_3V3FMC'




max. current: 0.5A
not dedicated for FMC connector


external source through
ATX main power connector



max. current: 6A

Enable by SC CPLD U5, bank 1, pin 51
Signal: 'EN_FMC_VADJ'

set voltage FMC_VADJ by DIP switch S1

FMC connector J2 Cooling Fan:

Fan DesignatorEnable SignalNotes

Enable by SC CPLD U5, bank 0, pin 78
Signal: 'FAN_FMC_EN'


PCI Express Interface

The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots and has a data transmission capability which meets PCIe Gen. 2 with 4 GTX lanes routed to the PCIe interface.

Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

LaneBankTypeSignal NamePCIe Connector PinFPGA Pin
  • PER3_P
  • PER3_N
  • PET3_P
  • PET3_N
  • J1-A29
  • J1-A30
  • J1-B27
  • J1-B28
  • MGTXTXP0_115, P2
  • MGTXTXN0_115, P1
  • MGTXRXP0_115, R4
  • MGTXRXN0_115, R3
  • PER2_P
  • PER2_N
  • PET2_P
  • PET2_N
  • J1-A25
  • J1-A26
  • J1-B23
  • J1-B24
  • MGTXTXP1_115, M2
  • MGTXTXN1_115, M1
  • MGTXRXP1_115, N4
  • MGTXRXN1_115, N3
  • PER1_P
  • PER1_N
  • PET1_P
  • PET1_N
  • J1-A21
  • J1-A22
  • J1-B19
  • J1-B20
  • MGTXTXP2_115, K2
  • MGTXTXN2_115, K1
  • MGTXRXP2_115, L4
  • MGTXRXN2_115, L3
  • PER0_P
  • PER0_N
  • PET0_P
  • PET0_N
  • J1-A16
  • J1-A17
  • J1-B14
  • J1-B15
  • MGTXTXP3_115, H2
  • MGTXTXN3_115, H1
  • MGTXRXP3_115, J4
  • MGTXRXN3_115, J3

PCIeSignal Schematic NameConnected toPCIe connector pinFPGA PinNotes


MGT bank 115



External clock supplied by PCIe interface

JTAG Connectors

There are two JTAG connectors J8 and J9 available on the TEF1001 board:

JTAG InterfaceSignal Schematic NameJTAG Connector PinConnected to



Connector: J8

CPLD_JTAG_TMSJ8-1SC CPLD, bank 0, pin 90
CPLD_JTAG_TDIJ8-2SC CPLD, bank 0, pin 94
CPLD_JTAG_TDOJ8-3SC CPLD, bank 0, pin 95


SC CPLD, bank 0, pin 91



Connector: J9

FPGA_JTAG_TMSJ9-4FPGA, bank 0, pin N9
FPGA_JTAG_TCKJ9-6FPGA, bank 0, pin M8
FPGA_JTAG_TDOJ9-8FPGA, bank 0, pin N8
FPGA_JTAG_TDIJ9-10FPGA, bank 0, pin L8

FAN Connectors

The TEF1001 board offers one FAN connector for cooling the FPGA device and one built-in FAN for the FMC modules.

ConnectorSignal Schematic NamesConnected toNotes
4-Wire PWM FAN
connector J4,
12V power supply

'F1SENSE', pin J4-3
'F1PWM', pin J4-4

SC CPLD U5, pin 99
SC CPLD U5, pin 98

FPGA cooling FAN can be controlled via
I²C interface from FPGA,
see current SC CPLD firmware
2-pin FAN connector J6,
5V power supply
with TPS2051 Load Switch U25


(Load Switch U25, pin 4)

SC CPLD U5, pin 78

FMC cooling FAN

On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

System Controller CPLD

The System Controller CPLD (U5) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the board's SC CPLD or into its bitstream file.. Table below lists the SC CPLD I/O pins with their default configuration:

SC CPLD U5 Pins and InterfacesConnected toFunctionNotes
200MHZCLK_ENOscillator U1, pin 1Oscillator U1 control lineenables 200.0000MHz oscillator U1
BUTTONPush Button S2userReset Button
CPLD_JTAG_TDOheader J8, pin 3SC CPLD JTAG interfaceSC CPLD JTAG interface enabled when
DIP-switch S1-1 in ON-position
CPLD_JTAG_TDIheader J8, pin 2
CPLD_JTAG_TCKheader J8, pin 4
CPLD_JTAG_TMSheader J8, pin 1
JTAG_ENDIP switch S1-1
DDR3_SCLSO-DIMM U2. pin 202I²C bus of DDR3 SO-DIMMI²C interface connected to FPGA
DDR3_SDASO-DIMM U2. pin 200
PLL_SCLSi5338 U13, pin 12I²C bus of SI5338 quad clock PLLI²C interface connected to FPGA
PLL_SDASi5338 U13, pin 19
PCIE_RSTbPCIe J1, pin A11PCIe reset inputrefer to current SC CPLD firmware for functionality
FEX_DIR / FEX0 ... FEX11FPGA bank 14user GPIOrefer to current SC CPLD firmware for functionality
F1PWMFAN connector J4, pin 4FPGA FAN controlrefer to current SC CPLD firmware for functionality
F1SENSEFAN connector J4, pin 3
FAN_FMC_ENLoad Switch U25, pin 4FMC FAN enable
FMC_PG_C2MFMC J2, pin D1FMC control signalsrefer to current SC CPLD firmware for functionality
FMC_PG_M2CFMC J2, pin F1
FMC_SCLFMC J2, pin C30FMC I²CI²C connected to FPGA
FMC_SDAFMC J2, pin C31
FMC_TCKFMC J2, pin D29FMC JTAGrefer to current SC CPLD firmware for functionality
FMC_TDIFMC J2, pin D30
FMC_TDOFMC J2, pin D31
FMC_TMSFMC J2, pin D33
DONEFPGA bank 0, pin J7FPGA configuration signalPL configuration completed
PROGRAM_BFPGA bank 0, pin P6PL configuration reset signal
LED1Green LED D11LED status signalrefer to current SC CPLD firmware for functionality
FPGA_IIC_OEFPGA bank 14, pin F25SC CPLD works as I²C switch
with the FPGA as I²C-Master
and on-board peripherals as
I²C output enable
FPGA_IIC_SCLFPGA bank 14, pin G26I²C clock line
FPGA_IIC_SDAFPGA bank 14, pin G25I²C data line
EN_1V8DC-DC U20, pin 27Power controlenable signal DC-DC U20
PG_1V8DC-DC U20, pin 28power good signal DC-DC U20
EN_3V3FMCDC-DC U15, pin 27enable signal DC-DC U15
PG_3V3DC-DC U15, pin 28power good signal DC-DC U15
EN_FMC_VADJDC-DC U7, pin 52enable signal DC-DC U7
PG_FMC_VADJDC-DC U7, pin 46power good DC-DC U7


DC-DC U7, pin 45, 44, 43DCDC U7 power selection pin


DIP switch S1-2,
DIP switch S1-3,
DIP switch S1-4
Power selection of FMC_VADJ, forwarded
to DCDC U7
LTM_1V5_RUNDC-DC U3, pin F5enable signals of DCDC U3, U4 (LTM4676)
refer to current SC CPLD firmware for functionality
LTM_4V_RUNDC-DC U3, pin F5
LTM_SCLDC-DC U3 / U4, pin E6DCDC U3, U4 (LTM4676) I²C

I²C Address U3: 0x40

I²C Address U4: 0x4F

I²C interface of LTM4676 ICs
also accessible through header J10

LTM_SDADC-DC U3 / U4, pin D6
LTM1_ALERTDC-DC U4, pin E5DCDC U3, U4 (LTM4676) control,
active low
refer to current SC CPLD firmware for functionality
LTM_1V_IO0DC-DC U4, pin E4
LTM_1V_IO1DC-DC U4, pin F5
LTM_1V5_4V_IO0DC-DC U3, pin E4
LTM_1V5_4V_IO1DC-DC U3, pin F4


The TEF1001 board supports additional DDR3 ECC SO-DIMM via 204-pin socket U2. The DDR3 memory interface has a 64bit wide databus and is routed to the FPGA banks 32, 33 and 34.

The reference clock signal for the DDR3 interface is generated by the 200.0000MHz MEMS oscillator U1 and is applied to the FPGA bank 33.

There is also a I2C interface between the System Controller CPLD U5 and the DDR3 ECC SO-DIMM memory socket U2.

I²C InterfaceSchematic net namesConnected toI²C AddressNotes

'DDR3_SDA', pin 200
'DDR3_SCL', pin 202

SC CPLD U5, pin 42
SC CPLD U5, pin 43

module dependent-

It is important to use SO-DIMMs which provide ECC functionality. SO-DIMMs without ECC are not compatible with this board.

Quad SPI Flash Memory

A 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Quad SPI Flash memory interface is connected to the FPGA bank 14, QSPI clock is provided by FPGA config bank 0.

Signal NameQSPI Flash Memory U12 PinFPGA Pin
FLASH_QSPI_CSS, Pin 7Bank 14, Pin C23
FLASH_QSPI_D00DQ0, Pin 15Bank 14, Pin B24
FLASH_QSPI_D01DQ1, Pin 8Bank 14, Pin A25
FLASH_QSPI_D02DQ2, Pin 9Bank 14, Pin B22
FLASH_QSPI_D03DQ3, Pin 1Bank 14, Pin A22
FPGA_CFG_CCLKC, Pin 16Bank 0, Pin C8

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Programmable Clock Generator

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U13) to generate various reference clocks for the module.

Si5338A Pin
Signal Name / Description
Connected toDirectionNote



not connectedInput

not used

IN2-GNDInputnot used


Reference input clock

U3, pin 3Input25.000000 MHz oscillator U14, Si8208AI


-GNDInputI2C slave device address LSB



not connectedInputnot used
IN6-GNDInputnot used
SCLPLL_SCLSC CPLD U5, pin 8Input / Output

I²C interface muxed to FPGA

Slave address: 0x70.

SDAPLL_SDASC CPLD U5, pin 2Input / Output



U6, G24Output

Clock to PL bank 14

CLK1AMGTCLK_5338_PU6, H6Output

Clock to MGT bank 115,
AC decoupled

CLK2ACLK1_PU6, G22OutputClock to PL bank 14


U6, D23OutputClock to PL bank 14


The FPGA module has following reference clocking sources provided by on-board oscillators and FMC connector J2:

Clock SourceFrequencySignal Schematic NameClock DestinationNotes
U14, SiT8208AI25.000000 MHzCLKSi5338A PLL U13, pin 3 (IN3)-
U1, DSC1123DL5200.0000 MHzDDR3_CLK_PFPGA bank 33, pin AB11

Enable by SC CPLD U5, pin 30

Signal: '200MHzCLK_EN'

DDR3_CLK_NFPGA bank 33, pin AC11
FMC Connector J2-GBTCLK0_M2C_P, Pin J2-D4FPGA bank 116, pin D6reference clock to MGT bank 116
GBTCLK0_M2C_N, Pin J2-D5FPGA bank 116, pin D5
-GBTCLK1_M2C_P, Pin J2-B20FPGA bank 116, pin F6reference clock to MGT bank 116
GBTCLK1_M2C_N, Pin J2-B21FPGA bank 116, pin F5
-CLK0_M2C_P, Pin J2-H4FPGA bank 15, pin H17reference clock to PL bank 15
CLK0_M2C_N, Pin J2-H5FPGA bank 15, pin H18
-CLK1_M2C_P, Pin J2-G2FPGA bank 15, pin G17reference clock to PL bank 15
CLK1_M2C_N, Pin J2-G3FPGA bank 15, pin G18
-CLK2_BIDIR_P, Pin J2-K4FPGA bank 13, pin P23reference clock to PL bank 13
bidirectional clock line
CLK2_BIDIR_N, Pin J2-K5FPGA bank 13, pin N23
-CLK3_BIDIR_P, Pin J2-J2FPGA bank 13, pin R22reference clock to PL bank 13
bidirectional clock line
CLK3_BIDIR_N, Pin J2-J3FPGA bank 13, pin R23

On-board LEDs

LEDColorSignal Schematic nameConnected toDescription and Notes
D1GreenFPGA_LED1_VTFPGA bank 13, pin K25

LEDs D1 to D10 are available to user.

LED voltages are translated from FPGA bank 13 and 14
VCCO voltage FMC_VADJ to 3V3.

D2GreenFPGA_LED2_VTFPGA bank 13, pin K26
D3GreenFPGA_LED3_VTFPGA bank 13, pin P26
D4GreenFPGA_LED4_VTFPGA bank 13, pin R26
D5GreenFPGA_LED5_VTFPGA bank 13, pin N16
D6GreenFPGA_LED6_VTFPGA bank 14, pin J26
D7GreenFPGA_LED7_VTFPGA bank 14, pin H26
D8GreenFPGA_LED8_VTFPGA bank 14, pin E26
D9GreenFPGA_LED9_VTFPGA bank 14, pin A24
D10GreenFPGA_LED10_VTFPGA bank 15, pin F19
D11GreenLED1System Controller CPLD, bank 0, pin 76refer to current CPLD firmware for LED functionality

Configuration DIP-switch

There is one 4-bit DIP-witches S1 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:

DIP-switch S3Signal Schematic NameConnected toFunctionalityNotes
S1-1JTAG_ENSC CPLD U5, bank 1, pin 82enables JTAG interface of SC CPLD U5 in ON-positionSC CPLD programmable through JTAG header J8
S1-2VID0_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 71set 3bit code to adjust FMC_VADJ voltage

The FMC_VADJ voltage is provided by DCDC U7 EN5365QI,

the voltage can be adjusted from 0.8V to 3.3V in 7 steps:

Set DIP-switches as  bit pattern "S1-4 | S1-3 | S1-2:  FMC_VADJ":

0 | 0 | 0 :   3.3V
0 | 0 | 1 :   2.5V
0 | 1 | 0 :   1.8V
0 | 1 | 1 :   1.5V
1 | 0 | 0 :   1.25V
1 | 0 | 1 :   1.2V
1 | 1 | 0 :   0.8V
1 | 1 | 1 :   Reserved

S1-3VID1_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 63
S1-4VID2_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 62

Push Buttons

There is one push buttons available to the user connected to the SC CPLD U5:

ButtonConnected toFunctionNotes
S2SC CPLD U5, pin 77Global board ResetRefer to documentation of current SC CPLD firmware
for more detais.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current

 * TBD - To Be Determined soon with reference design setup.

It is recommended to connect the ATX connector J5 to a 12V power supply source with minimum current capability of 6A to provide a sufficient power source to the board. Only one power source is needed at the same time, the system disconnects automatically PCIe power supply from PCIe edge connector J1 if the board is powered by the ATX connector J5.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

Power-On Sequence

The TEF1001 board meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.
Some of the voltages are handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Bank Voltages

BankSchematic NameVoltageRangeNotes
01V81.8V-Config bank 0 fixed to 1.8V
12FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
13FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
141V81.8VHR: 1.2V to 3.3VPL bank 14 fixed to 1.8V
15FMC_VADJuserHR: 1.2V to 3.3VFMC_VADJ voltage ajustable by DIP switch S1
16VIO_B_FMCuserHR: 1.2V to 3.3VPL bank 16 fixed to 1.8V
321V51.5VHP: 1.2V to 1.8VDDR3 memory interface
331V51.5VHP: 1.2V to 1.8VDDR3 memory interface
341V51.5VHP: 1.2V to 1.8VDDR3 memory interface









MGT bank supply voltage

MGT bank auxiliary supply voltage

MGT bank termination circuits voltage

MGT banks with Xilinx GTX transceiver units

Power Rails

Connector / PinVoltageDirectionNotes
J4, pin 212VOutput4-wire PWM fan connector supply voltage
J6, pin 25VOutputCooling fan M1 supply voltage
J8, pin 63V3OutputVCCIO CPLD JTAG
J9, pin 21V8OutputVCCIO FPGA JTAG
J2, pin C35 / C3712VOutputFMC supply voltage
J2, pin D323V3OutputVCCIO FMC
J2, pin D36 / D38 / D39 / D403V3FMCOutputVCCIO FMC
J2, pin H1VREF_A_M2CInputVREF voltage for bank 13 / 15
J2, pin K1VREF_B_M2CInputVREF voltage for bank 16
J2, pin J39 / J40VIO_B_FMCInputPL I/O voltage bank 16 (VCCO)
J2, pin H40 / G39 / F40 / E39FMC_VADJOutputPL I/O voltage bank 12 / 13 / 15 (VCCO)
J1, pin B1 / B2 / B3 / A2 / A312V_input_BInput12V main power supply from PCIe connector
J5, pin 1 / 2 / 312V_input_AInputMain power supply connector

Technical Specifications

Absolute Maximum Ratings




Reference Document

VIN supply voltage



TPS6217 datasheet

Note: voltage limitations are not valid for connected FMC module and/or FPGA FAN

Supply voltage for HR I/O banks (VCCO)



VXilinx datasheet DS182

Supply voltage for HP I/O banks (VCCO)


2.000VXilinx datasheet DS182
I/O input voltage for HR I/O banks


VCCO + 0.500

VXilinx datasheet DS182

I/O input voltage for HP I/O banks


VCCO + 0.500

VXilinx datasheet DS182
Reference Voltage pin (VREF)-0.5002VXilinx datasheet DS182
Differential input voltage-0.52.625VXilinx datasheet DS182
I/O input voltage for SC CPLD U5-0.53.75VLattice MachXO2 Family datasheet
GTX transceiver reference clocks absolute input voltage-0.5001.320VXilinx datasheet DS182

GTX transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage



VXilinx datasheet DS182
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10-0.35.5VLTM4676A datasheet

Storage temperature




SML-P11 LED datasheet

Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage11.412.6V12V nominal, ANSI/VITA 57.1 power specification for FMC connector
Supply voltage for HR I/O banks (VCCO)1.140


VXilinx datasheet DS182

Supply voltage for HP I/O banks (VCCO)



VXilinx datasheet DS182

I/O input voltage for HR I/O banks


VCCO + 0.20VXilinx datasheet DS182
I/O input voltage for HP I/O banks-0.500VCCO + 0.20VXilinx datasheet DS182
Differential input voltage-0.22.625VXilinx datasheet DS182
I/O input voltage for SC CPLD U5-0.33.6VLattice MachXO2 Family datasheet
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J1003.3VVLTM4676A datasheet

Board Operating Temperature Range 1), 2)


board operating temperature range limited by FPGA SoC and on-board peripherals

1) Temperature range may vary depending on assembly options

2) The operating temperature range of the FPGA soC and on-board peripherals are junction and also ambient operating temperature ranges

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Please check also Xilinx datasheet DS182 for complete list of absolute maximum and recommended operating ratings.

Physical Dimensions

Variants Currently In Production

Trenz shop TEF1001 overview page
English pageGerman page

Revision History

Hardware Revision History



PCNDocumentation Link
-02current available board revision--


First production release

PCN-20180524 TEF1001-01TEF1001-01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


  • update picture
2018-10-24v.41Guillermo Herrera
  • Initial document