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Table of Contents

Overview

Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/carrier_boards/TEBA0841 for downloadable version of this manual and additional technical documentation of the product.

The Trenz Electronic TEBA0841 is a base-board for test- and evaluation-purposes, especially for the Multi-gigabit transceiver units of the TE0841 and TE0741 modules. Although this base-board is dedicated to these modules, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs. See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEBA0841 base-board.

This base-board provides also soldering-pads as place-holders for pin-headers as option to get access to the PL-IO-banks of the mounted SoM.

Key Features

Block Diagram


Figure 1: TEBA0841-01 Block Diagram

Main Components

  

Figure 2: 4 x 5 SoM carrier board TEBA0841-01

 

TEBA0841-01:

  1. Samtec Razor Beam™ LSHM-150 B2B connector JB1
  2. Samtec Razor Beam™ LSHM-150 B2B connector JB3
  3. Samtec Razor Beam™ LSHM-130 B2B connector JB2
  4. 6-pin header J26 for selecting PL IO-bank supply-voltage VCCIOA
  5. 6-pin header J27 for selecting PL IO-bank supply-voltage VCCIOD
  6. Micro USB Connector J12 (Device or OTG mode)
  7. JTAG/UART header JX1 ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
  8. User LED D1 (green)
  9. User LED D2 (red)
  10. SFP+ Connector J1
  11. 50-pin header soldering-pads J17 for access to SoM's IO-banks (LVDS-pairs possible)
  12. 50-pin header soldering-pads J20 for access to SoM's IO-banks (LVDS-pairs possible)
  13. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
  14. 10-pin header soldering-pads J4 for access to SoM's SDIO-port, if available

Interfaces and Pins

SFP+ Connector

On the TEBA0841 carrier board is a SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).

The RX-/TX-data-lanes are connected to B2B-connector JB2, the control-lines are connected to module's IO-pins on B2B-connector JB1 (MIO0-bank-pins in standard TE module's pin-assignment).

On this SFP+ connector, at both 4 x 5 SoMs TE0741 and TE0841 MGT-lane 3 is accessible.

The pin-assignment of the SFP connector is in detail as fellows:

SFP+ pinSFP+ pin Schematic NameB2BNote
Transmit Data + (pin 18)MGT_TX3_PJB2-26-
Transmit Data - (pin 19)MGT_TX3_NJB2-28-
Receive Data + (pin 13)MGT_RX3_PJB2-25-
Receive Data - (pin 12)MGT_RX3_NJB2-27-
Receive Fault (pin 2)MIO10JB1-96-
Receive disable (pin 3)not connected--
MOD-DEF2 (pin 4)MIO13JB1-983.3V pull-up, (usable I²C SDA/SCL-line)
MOD-DEF1 (pin 5)MIO12JB1-1003.3V pull-up, (usable I²C SDA/SCL-line)
MOD-DEF0 (pin 6)MIO11JB1-94-
RS0 (pin 7)not connected--
LOS (pin 8)MIO0JB1-88-
RS1 (pin 9)not connected--

Table 1: SFP+ connector pin-assignment

Looped-backed MGT-Lanes on B2B Connector JB1 and JB2

The TEBA0841 carrier board is mainly for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, 5 RX/TX differential pairs are bridged on-board, hence the transmitted data on this MGT-lanes flows back to their sources in a loop-back circuit without intentional processing or modification. 

The MGT-lane pins are bridged on-board as fellows, if 4 x 5 SoM TE0741 is mounted on carrier board:

MGT-laneB2B TX diff-pairB2B RX diff-pairB2B pins bridged
MGT-lane 0

JB2-8 (MGT_TX0_N)

JB2-10 (MGT_TX0_P)

JB2-7 (MGT_RX0_N)

JB2-9 (MGT_RX0_P)

JB2-7 to JB2-8

JB2-9 to JB2-10

MGT-lane 1

JB2-14 (MGT_TX1_N)

JB2-16 (MGT_TX1_P)

JB2-13 (MGT_RX1_N)

JB2-15 (MGT_RX1_P)

JB2-13 to JB2-14

JB2-15 to JB2-16

MGT-lane 2

JB2-20 (MGT_TX2_N)

JB2-22 (MGT_TX2_P)

JB2-19 (MGT_RX2_N)

JB2-21 (MGT_RX2_P)

JB2-19 to JB2-20

JB2-21 to JB2-22

MGT-lane 7

JB1-3 (MGT_TX7_P)

JB1-5 (MGT_TX7_N)

JB1-9 (MGT_RX7_P)

JB1-11 (MGT_RX7_N)

JB1-3 to JB1-9

JB1-5 to JB1-11

MGT-lane 6

JB1-15 (MGT_TX6_P)

JB1-17 (MGT_TX6_N)

JB1-21 (MGT_RX6_P)

JB1-23 (MGT_RX6_N)

JB1-15 to JB1-21

JB1-17 to JB1-23

Table 2: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0741.

Note: The MGT-lanes of the 4 x 5 SoM TE0841 have different designations. See Schematic of the particular module.

USB Interface

The TEBA0841 carrier board has one physical USB-connector J10, which is available as Micro-USB port. The USB interface J10 can be operated in Device- and OTG-modes. The Micro-USB port-pins are routed to the USB-OTG-interface on B2B-connector JB2. There are usually corresponding USB-PHYs on SoMs supported by the carrier board TEBA0841.

JTAG/UART Interface

The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1 or J3 with two additional pins (15,16) as LVDS-pair to supply the mounted 4 x 5 SoM with an external reference clock-signal.

This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, so the XMOD-FT2232H adapter-board TE0790 can be used in conjunction with the Carrier Board to program the mounted SoM via USB interface.

JX1 pinJX1 pin Schematic NameB2B J3 pinJ3 pin Schematic NameB2B
C (pin 4)TCKJB3-100 4TCKJB3-100
D (pin 8)TDOJB3-98 8TDOJB3-98
F (pin 10)TDIJB3-96 10TDIJB3-96
H (pin 12)TMSJB3-94 12TMSJB3-94
A (pin 3)MIO15JB1-86 (usable as UART RX/TX-line) 3MIO15JB1-86 (usable as UART RX/TX-line)
B (pin 7)MIO14JB1-91 (usable as UART RX/TX-line) 7MIO14JB1-91 (usable as UART RX/TX-line)
E (pin 9)BOOTMODEJB1-90 (JTAGSELECT) 9BOOTMODEJB1-90 (JTAGSELECT)
G (pin 11)RESINJB3-17 11RESINJB3-17
--- 15CLK0_NJB2-32 (MGT_CLK0_N, decoupling capacitator 100 nF)
--- 16CLK0_PJB2-34 (MGT_CLK0_P, decoupling capacitator 100 nF)

Table 3: JTAG header JX1 / J3 pin-assignment

On both interfaces (JX1, J3), the pins with the net-names MIO14 and MIO15 are available as user IO's which could be used as UART-interface for example.

LEDs

Two LEDs are present on the TEBB0714 base-board with following functionality:

 LED DesignatorColorPin Schematic NameB2B ConnectorIndicating
D1greenMIO9JB1-92available to user
D2redRLEDJB3-90available to user

Table 4: LED's functionality

Place Holders for Optional Pin-headers

The TEBA0841 base-board has place-holders with solder-pads to mount optional pin-headers capable to access the PL IO-bank pins of the mounted 4 x 5 SoM. With this user interfaces, a large quantity of IO's are also usable as LVDS-pairs and different VCCIO's are available to operate the IO's properly.

Following table gives a summary of the optional pin-headers of the base-board:

Connector DesignatorPin-header LayoutCount of IO'sCount of LVDS-pairsAvailable VCCIO'sInterfaces
J42-row 10-pin60

3.3V

M1.8VOUT (from mounted module)

SDIO (6 IO's allocated), if available on mounted 4 x 5 SoM.

Voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary
due to the different voltage levels of the Micro SD Card (3.3V) and MIO0-bank of the Xilinx Zynq-chip (1.8V).

J172-row 50-pin42 (Bank 13)21

3.3V

VCCIOD

-
J202-row 50-pin42 (Bank 35)21

3.3V

VCCIOA

-
J32-row 16-pin121

3.3V

JTAG (4 IO's allocated).

UART (2 IO's allocated).

Reference clock input MGT-CLK0 (1 LVDS-pair).

Table 5: Summary of optional pin-headers

Power

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

The external power-supply can be connected to the board by the following pins:

Connector3.3V pinGND pin
JX1

JX1-5, JX1-6,

JX1-1, JX1-2
J3J3-5, J3-6J3-1, J3-2
J4J4-5J4-1, J4-2
J20J20-5, J20-46J20-1 , J20-2 , J20-49 , J20-50
J17J17-5, J17-46J17-1 , J17-2 , J17-49 , J17-50

Table 4: Connector-pins capable for external 3.3V power-supply

Power-On Sequence

The PL IO-bank supply-voltages 1.8V, 2.5V and 3.3V will be available after the mounted module's 3.3V voltage level has reached stable state on B2B-connector pins JM2-10 and JM2-12, meaning that all on-module voltages have become stable and module is properly powered up.

Note: The DCDC-converters generating the supply-voltages have low current dropout.

 

Figure 3: Power-On sequence diagram

Configuring VCCIO 

On the TEBA0841 carrier board different VCCIO configurations can be chosen by the jumper J26 and J27.

The purpose of the jumper of the carrier board will be explained in the following sections.

Summary of VCCIO-configuration

On the TEBA0841 carrier board the PL IO-bank's supply voltages of the 4x5 SoM (VCCIOA, VCCIOD; see 4x5 Module Integration Guide) are connected to the base-board VCCIO-voltage VCCIOA and VCCIOD, which are selectable between the supply-voltages 1.8V, 2.5V and 3.3V via jumper J26 and J27.

Baseboard
Supply Voltages
Base-board B2B Connector PinsStandard Assignment of PL IO-bank Supply Voltages
on TE 4x5 Module's B2B Connectors Pins
VCCIOAJB1-10, JB1-12VCCIOA (JM1-9, JM1-11)
VCCIODJB2-8, JB2-10VCCIOD (JM2-7, JM2-9)

Table 5: base-board supply-voltages VCCIOA and VCCIOD

 

Note: The corresponding PL IO-voltage supply voltages of the 4x5 SoM to the selectable base-board voltage VCCIOA and VCCIOD are depending on the mounted 4x5 SoM and varying in order of the used model.

Refer to SoM's schematic to get information about the specific pin-assignment on module's B2B-connectors regarding PL IO-bank supply-voltages and to the 4x5 Module integration Guide for VCCIO voltage options.

 

Following table describes how to configure the base-board supply-voltages by jumpers:

Base-board Supply Voltages
vs Voltage-levels

VCCIOAVCCIOD
1.8VJ26: 1-2J27: 1-2
2.5VJ26: 3-4J27: 3-4
3.3VJ26: 5-6J27: 5-6

Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.

Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsNotes

Vin supply voltage

3.135

3.465

V

3.3V supply-voltage ± 5%

Storage Temperature

-55105

°C

Molex 74441-0001 Product Specification

Recommended Operating Conditions

 ParameterMinMaxUnitsNotes
Vin supply voltage3.1353.465V-

Physical Dimensions

 The dimensions are given in mm and mil (milli inch).

Figure 4: Physical Dimensions of the TEBA0841-01 carrier board

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

ca. 32 g - Plain board

Hardware Revision History

DateRevision

Notes

PCNDocumentation link
-01---

Hardware revision number is printed on the PCB board next to the model number separated by the dash.


Figure 5: Hardware revision Number

Document Change History

DateRevisionAuthorsDescription
2017-06-08
Ali Nasericurrent TRM for TEBA0841-01
2017-01-300.1

Ali Naseri

Initial document

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