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Table of Contents

Overview

Refer to https://shop.trenz-electronic.de/ee/Download/?path=Trenz_Electronic/TE0841 for downloadable version of this manual and additional technical documentation of the product.
 

The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale KU035 FPGA, 2 banks of 512 MByte DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

Block Diagram

Main Components

  

  1. Xilinx Kintex UltraScale FPGA, U1
  2. Ultra Performance Oscillator @25.000000 MHz, U3
  3. 12A PowerSoC DC-DC Converter (0.95V), U14
  4. 12A PowerSoC DC-DC Converter (0.95V), U7
  5. Low-jitter Precision LVDS Oscillator @200.0000 MHz, U11
  6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
  7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
  8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  11. Programmable quad clock generator, U2
  12. 32 MByte QSPI Flash, U6
  13. 4 Gbit DDR4 SDRAM, U4
  14. 4 Gbit DDR4 SDRAM, U5
  15. System Controller CPLD, U18
  16. Low-dropout (LDO) linear regulator (MGTAUX), U9
  17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Key Features

Additional assembly options for cost or performance optimization plus high volume prices are available on request.

Initial Delivery State

Storage device name

Content

Notes

OTP Flash area

Empty

 

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected from the SoCs I/O banks and B2B connectors: 

FPGA BankTypeB2B ConnectorI/O Signal CountVoltageNotes
64HRJM148 IOs, 24 LVDS pairsB64_VCCOSupplied by the baseboard.
65HRJM18 IOs3.3V 
224MGTJM13 lanes  
65HRJM34 IOs, 2 LVDS pairs3.3V 
66HPJM316 IOs, 8 LVDS pairsB66_VCCOSupplied by the baseboard
224MGTJM31 lane  
225MGTJM34 lanes  
67HPJM248 IOs, 24 LVDS pairsB67_VCCOSupplied by the baseboard
67HPJM22 IOsB67_VCCOSupplied by the baseboard
68HPJM218 IOs, 9 LVDS pairsB68_VCCOSupplied by the baseboard

For detailed information about the pin out, please refer to the Pin-out Tables. 

I2C Interface

There are two PL bank 65 IO pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.

Additionally, two PL bank 65 IO pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary IOs.

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

JTAG Signal

B2B Connector Pin

TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99
JTAGMODE pin 89 in B2B connector JM1 should be kept low or grounded for normal operation.

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
JTAGMODEInputJTAG selectLow for normal operation.
NRST_SC0InputReset 
SC1--Not used by default.
SC2--Not used by default.
SC3--Not used by default.
SC4--Not used by default.

LED's

LEDColorConnected toDescription and Notes
D1GreenSystem Controller CPLD, bank 3Exact function is defined by SC CPLD firmware.

On-board Peripherals

Processing System (PS) Peripherals

NameICIDPS7MIONotes
QSPI FlashN25Q256AU6   
PLL quad clock generatorSI5338AU2   

Clocking

Clock SignalFrequencySourceFPGANotes
-

25.000000 MHz

SiT8208 (U3), CLK-Reference clock input for Si5338 PLL quad clock generator.
CLK200M200.0000 MHzDSC1123 (U11), OUTR25/R26, bank 45 
CLK0User programmableSi5338 (U2), CLK3T24/T25, bank 45 
CLK1User programmableSi5338 (U2), CLK0R23/P23, bank 45 
MGT_CLK0Baseboard suppliedJM3-31, JM3-33Y5/Y6, bank 225Bank 225 MGTs clock source from baseboard.
MGT_CLK1User programmableSi5338 (U2), CLK1V5/V6, bank 225Bank 225 MGTs clock source from on-board PLL quad clock generator.
MGT_CLK2Baseboard suppliedJM3-32, JM3-34AD6/AD5, bank 224Bank 224 MGTs clock source from baseboard.
MGT_CLK3User programmableSi5338 (U2), CLK2AB6/AB5, bank 224Bank 224 MGTs clock source from on-board PLL quad clock generator.

Power and Power-On Sequence

Power Supply

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

Power Consumption

Power Input PinMax Current
VINTBD*
3.3VINTBD*

 * TBD - To be determined soon with reference design setup.

Power-On Sequence

For highest efficiency of on board DC-DC regulators, it is recommended ...

Power Rails

Voltages on B2B

Connectors

B2B JM1 Pins

B2B JM2 Pins

Input/Output

Notes
VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
B64_VCO9, 11-InputHR (High Range) bank voltage.
B66_VCO-1, 3InputHP (High Performance) bank voltage.
B67_VCO-7, 9InputHP (High Performance) bank voltage.
B68_VCO-5InputHP (High Performance) bank voltage.

VBAT_IN

79-InputRTC battery supply voltage.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage level.

Board to Board Connectors

Variants Currently In Production

Module Variant

FPGA Chip

PL Clock
TE0841-01-035-1CXCKU035-1SFVA784C 
TE0841-01-035-1I
XCKU035-1SFVA784I 
TE0841-01-035-2I
XCKU035-2SFVA784I 

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

  

V

-

Storage temperature

-40

+85

°C

-

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage    
Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

 All dimensions are given in millimeters.

   

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

47 g - Plain module.

9 g - Set of bolts and nuts.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2015-12-09

01

First production revision

-TE0841-01

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.


Document Change History

Date

Revision

Contributors

Description

2017-01-31
Jan Kumann
Initial document.

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