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Table of Contents |
Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and additional technical documentation of the product. |
The Trenz Electronic TE0720 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020) with up to 1 GB of DDR3/L SDRAM, 32MB of SPI flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. See also Variants Currently in Production section.
Additional assembly options are available for cost or performance optimization upon request.
Components and connections marked with dashed lines are optional or may be missing on some module variants, please contact us for additional information.
Storage device name | IC | Content | Notes |
---|---|---|---|
Quad SPI Flash | U7 | Empty | - |
eMMC NAND Flash | U15 | Empty | - |
11AA02E48T EEPROM | U17 | Pre-programmed globally unique, 48-bit node address (MAC) | - |
System Controller CPLD | U19 | Standard firmware. | Download firmware |
I/O signals connected to the SoC's IO bank and B2B connector:
Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
---|---|---|---|---|---|
13 | GPIO | JM2 | 48 I/Os, 24 LVDS pairs | VCCIO13 | |
13 | GPIO | JM2 | 2 I/Os | VCCIO13 | B13_IO0 and B13_IO25 |
33 | GPIO | JM2 | 18 I/Os, 9 LVDS pairs | VCCIO33 | |
34 | GPIO | JM3 | 36 I/Os, 18 LVDS pairs | VCCIO34 | |
35 | GPIO | JM1 | 48 I/Os, 24 LVDS pairs | VCCIO35 | |
500 | MIO | JM1 | 8 MIOs | 3.3V | |
501 | MIO | JM1 | 6 MIOs | 1.8V |
For detailed information about the pin-out, please refer to the Pin-out tables.
JTAG access to the Xilinx Zynq and to the System Controller CPLD is provided through B2B connector JM2.
JTAG Signal | B2B Connector Pin |
---|---|
TMS | JM2-93 |
TDI | JM2-95 |
TDO | JM2-97 |
TCK | JM2-99 |
JTAGMODE pin 89 in B2B connector JM1 is used to select which device is accessible. Low - Xilinx Zynq, High - System Controller CPLD. |
Special purpose pins are connected to System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | Default Configuration |
---|---|---|---|
RESIN | Input | Reset input | Active low reset input, default mapping forces POR_B reset to Zynq PS. |
PGOOD | Output | Power good | Active high when all on-module power supplies are working properly. |
MODE | Input | Boot mode | Force low for boot from the SD card. Latched at power-on only, not during soft reset! |
EN1 | Input | Power enable | High enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high. |
NOSEQ | Input | Power sequencing | Forces the 1.0V and 1.8V DC-DC converters always ON when high. |
JTAGMODE | Input | JTAG select | Keep low for FPGA JTAG access. |
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D2 | Green | LED1 | Controlled by System Controller CPLD firmware. |
D4 | Green | DONE | |
D5 | Red | LED2 | Controlled by System Controller CPLD firmware. |
Clock Signal | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS-CLK | 33.333333 MHz | U6 | PS_CLK_500 | PS subsystem main clock. |
OTG-RCLK | 52.000000 MHz | U14 | - | USB3320C reference clock. |
ETH-CLK | 25.000000 MHz | U9 | - | 88E1512 reference clock. |
MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes | |
---|---|---|---|---|---|---|---|---|
0 | GPIO | JM1-87 | - | 16..27 | ETH0 | - | RGMII | |
1 | QSPI0 | - | SPI-CS | 28..39 | USB0 | - | ULPI | |
2 | QSPI0 | - | SPI-DQ0 | 40 | SD0 | JM1-27 | B2B | |
3 | QSPI0 | - | SPI-DQ1 | 41 | SD0 | JM1-25 | B2B | |
4 | QSPI0 | - | SPI-DQ2 | 42 | SD0 | JM1-23 | B2B | |
5 | QSPI0 | - | SPI-DQ3 | 43 | SD0 | JM1-21 | B2B | |
6 | QSPI0 | - | SPI-SCK | 44 | SD0 | JM1-19 | B2B | |
7 | GPIO | - | SC CPLD pin P11 | 45 | SD0 | JM1-17 | B2B | |
8 | - | - | 3.3V | 46 | SD1 | - | MMC-D0 | |
9 | - | JM1-91 | B2B | 47 | SD1 | - | MMC-CMD | |
10 | - | JM1-95 | B2B | 48 | SD1 | - | MMC-CLK | |
11 | - | JM1-93 | B2B | 49 | SD1 | - | MMC-D1 | |
12 | - | JM1-99 | B2B | 50 | SD1 | - | MMC-D2 | |
13 | - | JM1-97 | B2B | 51 | SD1 | - | MMC-D3 | |
14 | - | JM1-92 | B2B | 52 | ETH0 | - | MDC | |
15 | - | JM1-85 | B2B | 53 | ETH0 | - | MDIO |
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).
Ethernet PHY connection
PHY Pin | Zynq PS | Notes |
---|---|---|
MDC | MIO52 | Routed to System Controller CPLD pin L14. |
MDIO | MIO53 | Routed to System Controller CPLD pin K14. |
LED0 | - | Routed to System Controller CPLD pin F14. |
LED1 | - | Routed to System Controller CPLD pin D12. |
LED2/Interrupt | - | Routed to System Controller CPLD pin C13. |
CONFIG | - | Routed to System Controller CPLD pin C14. |
RESETn | MIO50 | - |
RGMII | MIO16..MIO27 | - |
SGMII | - | Routed to B2B connector JM3. |
MDI | - | Routed to B2B connector JM1. |
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501. The I/O voltage is fixed at 1.8V and reference clock input of the PHY is supplied from the on-board 52.000000 MHz oscillator (U14).
USB PHY connection
USB PHY Pin | ZYNQ Pin | SC CPLD Pin | B2B Name | Notes |
---|---|---|---|---|
REFCLK | - | - | - | 52.000000 MHz reference clock from on-board oscillator (U14). |
REFSEL0..2 | - | - | - | Reference clock frequency select, all set to GND selects 52.000000 MHz. |
RESETB | - | B14, bank 1 | - | Active low reset. |
CLKOUT | MIO36 | - | - | ULPI output clock mode. |
DP, DM | - | OTG-D_P, OTG-D_N | USB data lines. | |
CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. | |
VBUS | - | - | USB-VBUS | Connect to USB VBUS via a series of resistors, see reference schematic. |
ID | - | - | OTG-ID | For A-device connect to the ground, for B-device leave floating. |
SPK_L | - | M5, bank 2 | - | In USB audio mode a switch connects the DM pin to the SPK_L pin. |
SPK_R | - | M8, bank 2 | - | In USB audio mode a switch connects the DP pin to the SPK_R pin. |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.
On-board I2C devices are connected to the System Controller CPLD, device slave addresses are listed in the table below:
I2C Device | I2C Address | IC | Notes |
---|---|---|---|
ISL12020M RTC | 0x6F | U20 | RTC registers. |
ISL12020M SRAM | 0x57 | U20 | Battery backed RAM in RTC IC. |
LSM303D | 0x1D | U22 | Optional, not soldered on current production variants. |
By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.
MODE Signal State | Boot Mode |
---|---|
High or open | SD Card |
Low or connected to the ground | QSPI |
On-board QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Name | IC | ID | PS7 | MIO Bank | MIO | Notes |
---|---|---|---|---|---|---|
Gigabit Ethernet | 88E1512 | U8 | ETH0 | 501 | MIO16..27 MIO52..53 | MIO52 and MIO53 are also connected to the System Controller CPLD. |
USB OTG | USB3320C | U18 | USB0 | 501 | MIO28..39 | |
SPI Flash | S25FL256SAGBHI20 | U7 | QSPI0 | 500 | MIO1..6 | |
eMMC Flash | MTFC4GMVEA-4M IT1) | U15 | SD1 | 501 | MIO46..51 |
1) Different make and model may be installed on different module variants.
Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD and contains globally unique 48-bit node address which is compatible with EUI-48TM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
---|---|
VIN | TBD* |
3.3VIN | TBD* |
* TBD - To Be Determined soon with reference design setup.
Power Distribution Diagram
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered). |
For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See also Xilinx datasheet DS187 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0720 module.
NOSEQ input signal
NOSEQ input signal from the carrier board can be used to control output of the two DC-DC converters U1 and U3. It works in conjunction with the System Controller CPLD firmware controlled ON_1V0 and ON_1V8 input signals of the U21 and U25 gate ICs.
If NOSEQ input signal from the carrier board is low (logical 0), signals ON_1V0 and ON_1V8 can be driven by System Controller CPLD to control outputs of the U1 and U3 DC-DC converters. | If NOSEQ input signal from the carrier board is high (logical 1), state of the ON_1V0 and ON_1V8 signals is irrelevant and DC-DC converters U1 and U3 outputs are always enabled. |
Initial state of the ON_1V0 and ON_1V8 signals and therefore also functionality of the NOSEQ signal depend on the System Controller CPLD firmware. |
B2B Name | B2B JM1 Pins | B2B JM2 Pins | Direction | Note |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from carrier board. |
3.3VIN | 13, 15 | 91 | Input | Supply voltage from carrier board. JM2-91 is VREF_JTAG. |
VCCIO35 | 9, 11 | - | Input | High range bank voltage from carrier board. |
VCCIO33 | - | 5 | Input | High range bank voltage from carrier board. |
VCCIO13 | - | 7, 9 | Input | High range bank voltage from carrier board. |
VCCIO34 | - | 1, 3 | Input | High range bank voltage from carrier board. |
VBAT_IN | 79 | - | Input | RTC battery-buffer supply voltage. |
3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
1.8V | 39 | - | Output | Internal 1.8V voltage level. |
1.5V 1) | - | 19 | Output | Internal 1.5V voltage level. |
1) In case of module variant of TE0720-03-L1IF which uses Xilinx Zynq XC7Z020-L1CLG484I chip with lower power consumption, power rails named 1.5V and VCCO_DDR_502 voltage is actually 1.35V. To achieve this, a resistor with different value is used for R4 (see schematic of the TE0720-03-L1IF for more information).
Bank | Schematic Name | Voltage | Notes |
---|---|---|---|
500 | 3.3V, VCCO_MIO0_500 | 3.3V | |
501 | 1.8V, VCCO_MIO1_501 | 1.8V | |
502 | 1.5V, VCCO_DDR_502 | 1.5V | |
0 Config | 3.3V | 3.3V | |
13 HR | VCCO13 | 1.2V to 3.3V | Supplied by the carrier board. |
33 HR | VCCIO33 | 1.2V to 3.3V | Supplied by the carrier board. |
34 HR | VCCIO34 | 1.2V to 3.3V | Supplied by the carrier board. |
35 HR | VCCIO35 | 1.2V to 3.3V | Supplied by the carrier board. |
Module Variant | Zynq SoC | RAM | eMMC Size | Temperature Range | B2B Connector Height |
---|---|---|---|---|---|
TE0720-03-2IF | XC7Z020-2CLG484I | 1 GByte | 4 GByte | Industrial | 4.0 mm |
TE0720-03-2IFC3 | XC7Z020-2CLG484I | 1 GByte | 4 GByte | Industrial | 2.5 mm |
TE0720-03-2IFC8 | XC7Z020-2CLG484I | 1 GByte | 32 GByte | Industrial | 4.0 mm |
TE0720-03-L1IF | XC7Z020-L1CLG484I | 512 MByte | 4 GByte | Industrial | 4.0 mm |
TE0720-03-1CF | XC7Z020-1CLG484C | 1 GByte | 4 GByte | Commercial | 4.0 mm |
TE0720-03-1CR | XC7Z020-1CLG484C | 256 MByte | - | Commercial | 4.0 mm |
TE0720-03-14S-1C | XC7Z014S-1CLG484C | 1 GByte | 4 GByte | Commercial | 4.0 mm |
TE0720-03-1QF | XA7Z020-1CLG484Q | 1 GByte | 4 GByte | Automotive | 4.0 mm |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | -0.3 | 6.5 | V | EP53F8QI datasheet. |
3.3VIN supply voltage | -0.1 | 3.75 | V | TPS27082L and LCMXO2-1200HC datasheets. |
Supply voltage for PS MIO banks | -0.5 | 3.6 | V | See Xilinx DS187 datasheet. |
I/O input voltage for MIO banks | -0.4 | VCCO_MIO + 0.55 | V | See Xilinx DS187 datasheet. (VCCO_MIO0_500, VCCO_MIO1_501) |
Supply voltage for HR I/Os banks | -0.5 | 3.6 | V | See Xilinx DS187 datasheet. (VCCIO13, VCCIO33, VCCIO34, VCCIO35) |
I/O input voltage for HR I/O banks | -0.4 | VCCIO + 0.55 | V | See Xilinx DS187 datasheet. |
Storage temperature | -40 | +85 | °C | - |
Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed | -55 | +100 | °C | NB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C. |
Assembly variants for higher storage temperature range are available on request. |
Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings. |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | 2.5 | 5.5 | V | EN6347QI and EP53F8QI datasheets. |
3.3VIN supply voltage | 3.135 | 3.465 | V | 3.3V +/- 5%. |
Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
I/O input voltage for PS MIO banks | -0.20 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
Commercial grade: 0°C to +70°C.
Industrial and automotive grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
ca 23 g - Plain module
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2015-10-12 | 03 | TE0720-03 | ||
- | 02 | TE0720-02 | ||
- | 01 | Prototypes |
There is no hardware revision number marking on the module.
Date | Revision | Contributors | Description |
---|---|---|---|
2017-06-14 | Jan Kumann | Initial document. |