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Table of Contents |
Refer to https://wiki.trenz-electronic.de/display/PD/TE0841+TRM for online version of this manual and additional technical documentation of the product. |
The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale FPGA, 1 GByte of DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.
Additional assembly options for cost or performance optimization plus high volume prices are available on request.
Figure 1: TE0841-01 block diagram.
Figure 2: TE0841-01 main components.
Storage device name | Content | Notes |
---|---|---|
OTP Flash area | Empty | Not programmed. |
Quad clock generator |
Table 1: TE0841-01 module initial delivery state of programmable on-board devices.
Table below lists bank number, bank type, B2B connection, I/O signal/LVDS pair count and power source for each FPGA PL I/O bank connected to the B2B connectors:
FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
---|---|---|---|---|---|
64 | HR | JM1 | 48 IOs, 24 LVDS pairs | B64_VCCO | B64_VCCO supplied by the carrier board. |
65 | HR | JM1 | 8 IOs | 3.3V | Powered by on-module power supply. |
65 | HR | JM3 | 4 IOs, 2 LVDS pairs | 3.3V | Powered by on-module power supply. |
66 | HP | JM3 | 16 IOs, 8 LVDS pairs | B66_VCCO | B66_VCCO supplied by the carrier board |
67 | HP | JM2 | 48 IOs, 24 LVDS pairs | B67_VCCO | B67_VCCO supplied by the carrier board |
67 | HP | JM2 | 2 IOs | B67_VCCO | B67_VCCO supplied by the carrier board |
68 | HP | JM2 | 18 IOs, 9 LVDS pairs | B68_VCCO | B68_VCCO supplied by the carrier board |
Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors.
For detailed information about the pin out, please refer to the Pin-out Tables.
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
---|---|---|---|---|---|
0 | 225 | GTH |
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1 | 225 | GTH |
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2 | 225 | GTH |
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3 | 225 | GTH |
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4 | 224 | GTH |
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5 | 224 | GTH |
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6 | 224 | GTH |
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7 | 224 | GTH |
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Table 3: MGT lanes
Below are listed MGT banks reference clock sources.
Clock signal | Bank | Source | FPGA Pin | Notes |
---|---|---|---|---|
MGT_CLK0_P | 225 | B2B, JM3-33 | MGTREFCLK0P_225, Y6 | Supplied by the carrier board. |
MGT_CLK0_N | 225 | B2B, JM3-31 | MGTREFCLK0N_225, Y5 | Supplied by the carrier board. |
MGT_CLK1_P | 225 | U2, CLK1B | MGTREFCLK1P_225, V6 | On-board Si5338A. |
MGT_CLK1_N | 225 | U2, CLK1A | MGTREFCLK1N_225, V5 | On-board Si5338A. |
MGT_CLK2_P | 224 | B2B, JM3-34 | MGTREFCLK2P_224, AD6 | Supplied by the carrier board. |
MGT_CLK2_N | 224 | B2B, JM3-32 | MGTREFCLK2N_224, AD5 | Supplied by the carrier board. |
MGT_CLK3_P | 224 | U2, CLK2B | MGTREFCLK3P_224, AB6 | On-board Si5338A. |
MGT_CLK3_N | 224 | U2, CLK2B | MGTREFCLK3N_224, AB5 | On-board Si5338A. |
Table 4: MGT reference clock sources.
JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.
JTAG Signal | B2B Connector Pin |
---|---|
TMS | JM2-93 |
TDI | JM2-95 |
TDO | JM2-97 |
TCK | JM2-99 |
Table 5: JTAG interface signals.
JTAGMODE pin 89 in B2B connector JM1 should be set low or grounded for normal operation. |
Special purpose pins are connected to the System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | Default Configuration |
---|---|---|---|
JTAGMODE | Input | JTAG select | Low for normal operation. |
NRST_SC0 | Input | Reset | |
SC1 | - | - | Not used by default. |
SC2 | - | - | Not used by default. |
SC3 | - | - | Not used by default. |
SC4 | - | - | Not used by default. |
Table 6: System Controller CPLD I/O pins.
Quad SPI interface is connected to the FPGA configuration bank 0.
Signal Name | U6 Pin | FPGA Pin |
---|---|---|
SPI_CS | C2 | RDWR_FCS_B_0, AH7 |
SPI_D0 | D3 | D00_MOSI_0, AA7 |
SPI_D1 | D2 | D01_DIN_0, Y7 |
SPI_D2 | C4 | D02_0, U7 |
SPI_D3 | D4 | D03_0, V7 |
SPI_CLK | B2 | CCLK_0, V11 |
Table 7: Quad SPI interface signals and connections.
There are two PL bank 65 I/O pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.
Additionally, two PL bank 65 I/O pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary I/Os.
The System Controller CPLD (U18) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Module has Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate .
Si5338A Pin | Signal Name / Description | Connected To | Direction | Note |
---|---|---|---|---|
IN1 | - | Not connected. | Input | Not used. |
IN2 | - | GND | Input | Not used. |
IN3 | Reference input clock. | U3, pin 3 | Input | 25.000000 MHz oscillator, Si8208AI. |
IN4 | - | GND | Input | I2C slave device address LSB. |
IN5 | - | Not connected. | Input | Not used. |
IN6 | - | GND | Input | Not used. |
CLK0A | CLK1_P | U1, R23 | Output | FPGA bank 45. |
CLK0B | CLK1_N | U1, P23 | Output | FPGA bank 45. |
CLK1A | MGT_CLK1_N | U1, V5 | Output | FPGA MGT bank 225 reference clock. |
CLK1B | MGT_CLK1_P | U1, V6 | Output | FPGA MGT bank 225 reference clock. |
CLK2A | MGT_CLK3_N | U1, AB5 | Output | FPGA MGT bank 224 reference clock. |
CLK2B | MGT_CLK3_P | U1, AB6 | Output | FPGA MGT bank 224 reference clock. |
CLK3A | CLK0_P | U1, pin T24 | Output | FPGA bank 45. |
CLK3B | CLK0_N | U1, pin T25 | Output | FPGA bank 45. |
Table 8: Programmable quad PLL clock generator inputs and outputs.
The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
Clock Source | Frequency | Signal Name | Clock Destination |
---|---|---|---|
U3, SiT8208AI | 25.000000 MHz | CLK | U2, pin 3 (IN3) |
U11, DSC1123DL5 | 200.0000 MHz | CLK200M_P | U1, pin R25 |
U11, DSC1123DL5 | 200.0000 MHz | CLK200M_N | U1, pin R26 |
B2B, JM3-31 | User | MGT_CLK0_N | U1, pin Y5 |
B2B, JM3-33 | User | MGT_CLK0_P | U1, pin Y6 |
B2B, JM3-32 | User | MGT_CLK2_N | U1, pin AD5 |
B2B, JM3-34 | User | MGT_CLK2_P | U1, pin AD6 |
Table 9: Reference clock signals.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Green | System Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
Table 10: On-board LEDs.
Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
---|---|
VIN | TBD* |
3.3VIN | TBD* |
Table 11: Typical power consumption.
* TBD - To be determined.
For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See also Xilinx datasheet DS892 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0720 module.
Voltages on B2B Connectors | B2B JM1 Pins | B2B JM2 Pins | Input/Output | Notes |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage. |
3.3VIN | 13, 15 | - | Input | Supply voltage. |
B64_VCO | 9, 11 | - | Input | HR (High Range) bank voltage. |
B66_VCO | - | 1, 3 | Input | HP (High Performance) bank voltage. |
B67_VCO | - | 7, 9 | Input | HP (High Performance) bank voltage. |
B68_VCO | - | 5 | Input | HP (High Performance) bank voltage. |
VBAT_IN | 79 | - | Input | RTC battery supply voltage. |
3.3V | - | 10, 12, 91 | Output | Module on-board 3.3V voltage level. |
Table 12: Module power rails.
Module Variant | FPGA Chip | Temperature Range |
---|---|---|
TE0841-01-035-1C | XCKU035-1SFVA784C | Commercial |
TE0841-01-035-1I | XCKU035-1SFVA784I | Industrial |
TE0841-01-035-2I | XCKU035-2SFVA784I | Industrial |
TE0841-01-040-1C | XCKU040-1SFVA784C | Commercial |
TE0841-01-040-1I | XCKU040-1SFVA784I | Industrial |
Table 13: Module variants.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | V | - | ||
Supply voltage for HR I/O banks (VCCO) | –0.500 | 3.400 | V | See Xilinx datasheet DS892. |
Supply voltage for HP I/O banks (VCCO) | –0.500 | 2.000 | V | See Xilinx datasheet DS892. |
I/O input voltage for HR I/O banks | –0.400 | VCCO + 0.550 | V | See Xilinx datasheet DS892. |
I/O input voltage for HP I/O banks | –0.550 | VCCO + 0.550 | V | See Xilinx datasheet DS892. |
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2) | -0.500 | 1.320 | V | See Xilinx datasheet DS892. |
GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.500 | 1.260 | V | See Xilinx datasheet DS892. |
Storage temperature | -40 | +85 | °C | - |
Table 14: Module absolute maximum ratings.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | V | |||
Supply voltage for HR I/O banks (VCCO) | 1.140 | 3.400 | V | See Xilinx datasheet DS892. |
Supply voltage for HP I/O banks (VCCO) | 0.950 | 1.890 | V | See Xilinx datasheet DS892. |
I/O input voltage | –0.200 | VCCO + 0.20 | V | See Xilinx datasheet DS892. |
Table 15: Module recommended operating conditions.
Assembly variants for higher storage temperature range are available on request. |
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Figure 3: Module physical dimensions.
47 g - Plain module.
9 g - Set of bolts and nuts.
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2015-12-09 | 01 | First production revision | - | TE0841-01 |
Table 16: Hardware revision history.
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Figure 4: Module hardware revision number.
Date | Revision | Contributors | Description |
---|---|---|---|
Jan Kumann | Initial document. |
Table 17: Document change history.