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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

Overview

Firmware for PCB CPLD with designator U6. Second CPLD Device in Chain: LCMX02-256HC

Watchdog do not work correctly on all modules with Firmware released before 2017.08.22. Please update Firmware on CPLD. For questions, write to Trenz Electronic support.

2 Firmware variants with swapped external reset input and output available.

Public Docs > TE0729 CPLD > BD-WD_TEBF0729_REV02_ORG.png

Figure1: Firmware for TEB0729 without modification,

J2-89 externel reset input
J2-91 external reset output

Public Docs > TE0729 CPLD > BD-WD_TEBF0729_REV02_mod.png

Figure2: Firmware for TEB0729 with modification,

J2-89 external reset output
J2-91 externel reset input

Feature Summary

Boot Mode
JTAG connection
Power Management
Watchdog Management

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD Name	Direction	Pin	Description
BOARD_STAT	out	23	STATUS to B2B
BOOT_MODE1	in	28	Boot Mode Pin from B2B
BOOT_MODE2	in	27	Boot Mode Pin from B2B
BOOT1	out	13	Boot Mode Pin to FPGA (MIO4)
BOOT2	out	12	Boot Mode Pin to FPGA (MIO5)
EN_3V3	out	25	Enable 3.3V Switch
F_TCK	out	8	JTAG to FPGA
F_TDI	out	9	JTAG to FPGA
F_TDO	in	11	JTAG from FPGA
F_TMS	out	10	JTAG to FPGA
FPGA_IO	out	5	Status to FPGA
JTAGSEL	---	26	Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to FPGA, one: CPLD access)
nRST	inout	16	External Reset. Direction Firmware depends
nRST_IN	inout	4	External Reset. Direction Firmware depends
PS_POR_B	in	14	Reset from Watchdog to FPGA
TCK	in	30	JTAG from B2B
TDI	in	32	JTAG from B2B
TDO	out	1	JTAG to B2B
TMS	in	29	JTAG from B2B
WD_EN	in	21	Watchdog PL I/O
WD_HIT	in	20	Watchdog PL I/O
WDI	out	17	Watchdog trigger to external Watchdog IC

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGSEL (logical one for CPLD, logical zero for FPGA) on J2-111.

Power

3.3V (EN_3V3) is enabled.

Boot Mode

Boot Mode Pins routed through the CPLD. MIO2 and MIO3 are connected to GND via resistor.

Pin	FPGA IO	Value
BOOT1 (BMODE1)	MIO4	0	1	0	1
BOOT2 (BMODE2)	MIO5	0	0	1	1
Boot Modus		JTAG	not supported	QSPI	SD

Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV01 to REV02

Bugfix for TE0729-REV02 Watchdog support
Add 2 Variants for TEB0729-REV02 and TE0729-REV02_MOD support
Change Pin FGPA_IO direction
Change Pin BOARD_STAT output configuration

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Date	Document Revision	CPLD Firmware Revision	Supported PCB Revision	Description
		REV02	REV02	Work in progress
2017-06-07	v.1	REV02	REV02	Initial release
	All

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