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Table of Contents

Overview

Refer to https://wiki.trenz-electronic.de/display/DRAFT/TE0723+TRM for downloadable version of this manual and additional technical documentation of the product.
 

The Trenz Electronic TE0723 is a Arduino compatible FPGA module based on the Xilinx Zynq XC7Z010 SoC.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0723 block diagram.

Main Components

Figure 2: Main components of the TE0723 module.

  1. Xilinx Zynq XC7Z010 SoC, U1
  2. 4 Gbit DDR3L 256M x 16 SDRAM, U2
  3. 16 MByte quad SPI Flash memory, U5
  4. High-speed CMOS logic analog multiplexer/demultiplexer, U10

  5. 1 MHz low-power operational amplifier, U11
  6. Dual high-speed USB to multipurpose UART/FIFO, U3
  7. 0.5A dual-channel current-limited power switch, U21
  8. Low-power programmable oscillator @ 12.000000 MHz, U7
  9. 2-Kbit Microwire compatible serial EEPROM, U6
  10. 10-pin header, J1
  11. 8-pin header, J2
  12. 10-pin header, J3
  13. Analog input header, J4
  14. 2 x 4-pin header, J5
  15. PMod 2x6 interface header, J6
  16. USB host mode jumper, J7
  17. Micro USB 2.0 Type-B receptacle, J8
  18. Micro USB 2.0 Type-B receptacle, J9
  19. Micro SD card connector with detect signal, J10
  20. Analog input select jumper, J11
  21. 5V supply power input, J12
  22. Reset switch, S1
  23. Red LED, D2
  24. Green LED, D6
  25. Green LED, D7
  26. Ultra-low supply-current voltage monitor, U23
  27. 1A PowerSoC DC-DC converter (3.3 V), U20

  28. 1A PowerSoC DC-DC converter (1.8 V, U19
  29. 1A PowerSoC DC-DC converter (1.35 V), U16
  30. Hi-speed USB 2.0 ULPI transceiver, U18
  31. Low-power programmable oscillator @ 52.000000 MHz, U14
  32. 1A PowerSoC DC-DC converter (1.0 V), U17
  33. JTAG interface testpoints, TP1-TP4

Initial Delivery State

Storage device name

IC

Content

Notes

Quad SPI Flash

U5

Empty

 
Microwire serial EEPROMU6Empty 

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

The 7 boot mode strapping pins on the TE0723 module are set to boot the system from quad SPI Flash only. For additional information refer to the TE0723 schematic and Xilinx UG585 Zynq-7000 All Programmable SoC Technical Reference Manual section "Boot Mode Pin Settings".

Signals, Interfaces and Pins

I/O Signals

List of I/O signals between PS/PL banks and external connectors:

BankTypeConnectorSignal CountVoltageNotes
34HRJ163.3D8 .. 13, SDA, SCL
34HRJ283.3D2 .. 7, RXD, TXD
34HRJ683.3PIO01 .. PIO08
35HRJ473.3

AIN0 .. 5

35HRJ513.3ESP_GPIO2
500MIOJ1063.3SDCARD
501MIOJ543.3ESP_RXD, ESP_TXD, ESP_GPIO0, MOD_RST

Table x: .

JTAG Interface

JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.

Quad SPI Interface

Following line is just an example, change it to your needs.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

MIOSignal NameU14 Pin
1SPI-CSC2
2SPI-DQ0/M0D3
3SPI-DQ1/M1D2
4SPI-DQ2/M2C4
5SPI-DQ3/M3D4
6SPI-SCK/M4B2

Table x: Quad SPI interface signals and connections.

SD Card Interface

TE0723 module has on-board SD Card socket (J10) with card detect switch wired to the SoC PS MIO bank 500.


Zynq SoC's PinConnected ToSignal Name
MIO0J10-9Card detect switch
MIO10J10-7DAT0
MIO11J10-3CMD
MIO12J10-5CLK
MIO13J10-8DAT1
MIO14J10-1DAT3
MIO15J10-2CD/DAT3

USB Interface


Zynq SoC's PinConnected ToSignal Name
MIO28U18-7OTG-DATA4
MIO29U18-31OTG-DIR
MIO30U18-29OTG-STP
MIO31U18-2OTG-NXT
MIO32U18-3OTG-DATA0
MIO33U18-4OTG-DATA1
MIO34U18-5OTG-DATA2
MIO35U18-6OTG-DATA3
MIO36U18-1OTG-CLK
MIO37U18-9OTG-DATA5
MIO38U18-10OTG-DATA6
MIO39U18-13OTG-DATA7

ESP Wi-Fi Interface

Interface for the ESP8266 Wi-Fi module is provided through connector J5.

Zynq SoC's PinConnected ToSignal Name
MIO48J5-2ESP_TXD
MIO49J5-7ESP_RXD
MIO52J5-6MOD_RST
MIO53J5-3ESP_GPIO0

I2C Interface

I2C interface pins from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

Zynq SoC PinConnected ToSignal Name
R13J1-9SDA
P13J1-10SCL

Table x: .

On-board Peripherals

DDR Memory

TE0723 module has up to 512-MBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board quad SPI Flash memory S25FL127S (U5) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the Zynq SoC's PS, allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

Dual High-speed USB to Multipurpose UART/FIFO

FT2232H...

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).

Microwire Serial EEPROM

U36AA56BT-I/OT...

High-Speed Analog Multiplexer

Digitally controlled analog switch TI CD74HC4051...

Low-power Operational Amplifier

The Microchip Technology Inc. MCP6001...

Oscillators

The module has following reference clock signals provided by on-board oscillators:

SourceSignalFrequencyDestinationPin NameNotes
U14

PS_CLK

52.000000 MHz

U1

PS_CLK_500

Zynq SoC PS subsystem main clock.

U14

OTG-RCLK

52.000000 MHz

U18

REFCLK

USB3320C PHY reference clock.

U7OSCI12.000000 MHzU3OSCI

FT2232H oscillator input.

Table x: Reference clock signals.

On-board LEDs

There are three LEDs on-board TE0723:

LEDColorConnected ToDescription and Notes
D2RedMIO9, U1User LED.
D6

Green

U1, bank 34 pin G14FPGA_LED
D7

Green

3.3V

PWR_LED, power-on LED.

Table x: On-board LEDs.

Power and Power-On Sequence

Power Supply

Single 5V power supply with minimum current capability of 2A for system startup is recommended.

Power Consumption

TBD - To Be Determined.

Power-On Sequence

There is no specific power-on sequence, system will power-up itself if 5V is present either from J8, J9 or J12.

Variants Currently in Production

 Module VariantXilinx Zynq SoC

DDR3L

SDRAM

ARM

Cores

PL

Cells

LUTsFlip-Flops

Block

RAM

DSP

Slices

TE0723-02XC7Z010-1CLG225C128 MBytesDual-core28K17,6K35,2K2.1 MBytes80
TE0723-03MXC7Z010-1CLG225C512 MBytesDual-core28K17,6K35,2K2.1 MBytes80
TE0723-03-07S-1CXC7Z007S-1CLG225C512 MBytesSingle-core23K14,4K28,8K1.8 MBytes66

Table 8: Module variants.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.53.6

V

Xilinx datasheet DS187.

Storage temperature

-40

+85

°C

 

Table x: .

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
Supply voltage1.143.465 VXilinx datasheet DS187.

Table x: .

 

Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

Figure 3: TE0723 module physical dimensions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2016-07-1503 Click to see PCN.TE0723-03
2015-11-06
02  TE0723-02
 

01

 

  

Table x: TE0723 hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

Date

Revision

Contributors

Description

Jan Kumann

Initial document.

Table x: Document change history.

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