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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
Table of contents |
Firmware for PCB CPLD with designator U15. Second CPLD Device in Chain: LCMX02-256HC
See Document Change History
| Name / opt. VHD Name | Direction | Pin | Description |
|---|---|---|---|
| CPLD_IO1 | in | 12 | FPGA |
| CPLD_IO2 | out | 13 | FPGA |
| FMC_TCK | in | 30 | JTAG FMC J1 |
| FMC_TDI | in | 32 | JTAG FMC J1 |
| FMC_TDI_TOP | out | 28 | JTAG FMC J6 |
| FMC_TDO | out | 1 | JTAG FMC J1 |
| FMC_TDO_TOP | out | 27 | JTAG FMC J6 |
| FMC_TMS | in | 29 | JTAG FMC J1 |
| JTAGEN | in | 26 | Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over J7 Jumper |
| PRSNT_TOP | in | 25 | FMC J6 Present |
| TCK | out | 9 | JTAG FPGA |
| TDI | out | 11 | JTAG FPGA |
| TDO | in | 10 | JTAG FPGA |
| TMS | out | 8 | JTAG FPGA |
Connected to FPGA JTAG, if JTAGEN is zero. J6 FMC JTAG connector is add into JTAG Chain, if PRSNT_TOP is zero and CPLD_IO1 is one. PRSNT_TOP has internal pulldown on CPLD and CPLD_IO1 internal pullup. FPGA IOs are flouting, if FPGA is not programmed.
| JTAGEN | PRSNT_TOP | CPLD_IO1 | Description |
|---|---|---|---|
| 1 | don't care | don't care | CPLD is in the JTAG Chain |
| 0 | 0 | 0 | Only Module FPGA is in the JTAG Chain |
| 0 | 0 | 1 | Module FPGA and FMC J6 are in the JTAG Chain. Note FMC J6 Chain must be closed. |
| 0 | 1 | 0 | Only Module FPGA is in the JTAG Chain |
| 0 | 1 | 1 | Only Module FPGA is in the JTAG Chain |
CPLD_IO2 is one, if second module is present and CPLD_IO1 is set one, otherwise it's zero.
To get content of older revision got to "Change History" of this page and select older document revision number.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
|---|---|---|---|---|---|
| REV01 | REV01 | REV01 finished | ||
| 2017-09-09 | v.1 | REV01 | REV01 | Initial release | |
| All |