<!--
Template Revision 1.64
(HTML comments will be not displayed in the document, no need to remove them. For Template/Skeleton changes, increase Template Revision number. So we can check faster, if the TRM style is up to date).
-->

<!--
General Notes:
If some section is CPLD firmware dependent, make a note and if available link to the CPLD firmware description. It's in the TE shop download area in the corresponding module -> revision -> firmware folder.
-->

<!--
General Notes:
Designate all graphics and pictures with a number and a description. For example "Figure 1: TE07xx-xx Block Diagram" or "Table 1: Initial delivery state". "Figure x" and "Table x" have to be formatted to bold.  
-->

Overview

Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/XMOD/TE0790 for downloadable version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0790 is an universal USB2.0 to JTAG, UART and GPIO adapter based on the FTDI FT2232H USB2 IC. The adapter board converts signals from USB2.0 to standard serial or parallel interfaces of Embedded Systems like JTAG, SPI, I²C and UART.

The board is equipped with a programmable System Controller CPLD provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family) to control the signals of the configured interfaces. The data stream of the USB2.0 port can be also converted to 8 independent GPIO's or used as FIFO.

Key Features

• Xmod form-factor
  • size: 20 x 25 mm
  • M3 mounting hole
• FT2232H
  • USB2.0 port High Speed (480 Mbps) and Full Speed (12 Mbps) compatible
  • Entire USB protocol handled on the chip
  • USB2.0 to JTAG, SPI and I²C conversion provided by the IC's Multi-Protocol Synchronous Serial Engine (MPSSE)
  • USB2.0 to UART conversion
  • Channel B UART RX/TX LED's
  • Mini-USB B connector (more rigid then micro-USB)
  • 93C56 EEPROM
• Lattice XO2-256 CPLD
  • on board programmable using Lattice tools
  • 8 universal I/O pins
  • VCCIO either 3.3V or user supplied (1.8 to 3.3V)
  • RED user LED
  • 12 MHz clock from on-board Oscillator
• LDO DCDC for optional USB power
• GREEN Power-on LED
• User button
• 4 position DIP switch
  • Choose CPLD program mode
  • FTDI EEPROM disable (not implemented in PCB REV 1)
  • Use VIO same as VCC
  • Use VCC from USB

Block Diagram

Figure 1: TE0790-02 block diagram.

Main Components

Figure 2: TE0790-02 main components.

1. FTDI FT2232H IC U4
2. 2x6 Pin Header (2.54mm, female), J2
3. Mini USB B Connector J4
4. Microchip 93AA56BT-I/OT Configuration EEPROM, U10
5. DIP-switch S2
6. Push button S1
7. Lattice Semiconductor LCMXO2-256HC System Controller CPLD, U1
8. SiTime SiT8008AI-73 oscillator @12MHz, U6
9. Green LED, D1 (Power)
10. Red LED, D4 (User)
11. Red LED, D3 (UART RX)
12. Red LED, D2 (UART TX)

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Signals, Interfaces and Pins

2x6 Pin Header

The 2x6 pin header (2.54mm grid size, female) J2 have to be connected to the corresponding pin header on the target system. The signal assignment of the pin header on the adapter board depends on the configuration of the System Controller CPLD firmware.

Basic pin assignment:

Table 2: Pin header J2 signal assignment.

The signals of the FTDI FT2232H chip are not directly connected to the pin header J2 but routed to the System Controller CPLD of the adapter board, which controls and by-passes the signals to the pin header J2.

Therefore, different signal assignments are made on the pin header J2 depending on the SC CPLD firmware:

Signal assignment on TE0790 CPLD - XMOD Standard:

Table 3: Pin header J2 signal assignment with standard configuration firmware.

Signal assignment on Standard with RXD-TXD Swapped:

This is the same as the standard configuration except that UART RXD and TXD pins are swapped.

Table 4: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware.

Signal assignment on TE0790 CPLD - XMOD DIP40:

On DIPFORTy, VIO Pin is connected with VDD 3.3V Pin.  UART RXD is connected to FPGA-Pin L13 and UART TXD to K15. Connect XMOD on the top-side (FPGA side) of the PCB.

Table 5: Pin header J2 signal assignment with DIPFORTy firmware.

USB Interface

The USB2.0 interface is provided by the FTDI  FT2232H chip accessible by the Mini-USB B connector J4. The entire USB protocol is handled on chip and compatible to USB2.0 High Speed (480 MBps) and Full Speed (12 MBps).

On-board Peripherals

FTDI FT2232H IC

The FTDI FT2232H chip provides a variety of industry standard serial or parallel interfaces. On the TE0790 adapter board at current available SC CPLD firmware the functions USB2.0 to JTAG, UART and user GPIO's.

By programing the firmware of the SC CPLD and special EEPROM configurations further further functionalities are available of the FTDI chip which converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H IC.

Configuration EEPROM

In order to work with Xilinx tools special order must be used, in that case the EEPROM is pre-programmed and serialized and will be recognized by all Xilinx tools (ISE/Impact/Chipscope, Vivado Programmer/SDK..).

System Controller CPLD

The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces.

Signals of the serial interfaces like JTAG, SPI and I²C are by-passed, forwarded and controlled by the System Controller CPLD.

The internal routing of the signals on the System Controller CPLD between the USB2.0 interface and pin header J2  depends on its configured firmware. Refer to the Resources Site of the TE0790 for more information about the currently available System Controller CPLD firmware and for download.

DIP-switch

The DIP-switch S2 is to set different modes of powering the on-board peripherals and their I/O supply voltages.

Further functionalities are to secure the EEPROM content and to enable configuring the SC CPLD by JTAG interface:

Table 6: DIP-switch S2 setting description.

The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches S2-3 and S2-4:

Table 7: DIP-switch S2 power setting description.

User Push Button

The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.

On-board LEDs

The on-board LEDs indicates system status data transmission activities:

Table 8: On-board LEDs.

Power and Power-On Sequence

Power supply of the adapter board

The adapter on-board's peripherals are powered with 3.3V as supply voltage. If 3.3V (VCC and VIO) is supplied only by the LDO DCDC U3 (S2-3 and S2-4 OFF), the I/O-pins of header J2 deliver max. ~100mA.

If module is powered from base then S2-4 (and most likely S2-3 (VIO) too) must be OFF.

Power Rails

Table 9: Module power rails.

Variants Currently In Production

Table 10: Module variants.

Variants with TE-0790-xxL do not include the ID String in EEPROM for direct support from Xilinx Vivado.

Technical Specifications

Absolute Maximum Ratings

Table 11: Module absolute maximum ratings.

Recommended Operating Conditions

Table 12: Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Physical Dimensions

• Module size: 24,65mm × 20,02mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard pin headers: 8.5 mm.

• PCB thickness: 1.75 mm.

• Highest part on PCB: approx. 8.75 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Figure 3: Module physical dimensions drawing.

Revision History

Hardware Revision History

Table 13: Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure 4: Module hardware revision number.

Document Change History

<!--
Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

Date	Revision	Contributors	Description
		Ali Naseri	initial document

Table 14: Document change history.

Disclaimer

02 Sept 2017