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General Notes:
If some section is CPLD firmware dependent, make a note and if available link to the CPLD firmware description. It's in the TE shop download area in the corresponding module -> revision -> firmware folder.

General Notes:
Designate all graphics and pictures with a number and a description. For example "Figure 1: TE07xx-xx Block Diagram" or "Table 1: Initial delivery state". "Figure x" and "Table x" have to be formatted to bold.  

Download Link: Go to Base Folder of the Module or Carrier, for example : https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0712
Use english URL "../en/..

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Table of Contents


Wiki Link: Go to Base Folder of the Module or Carrier, for example : https://wiki.trenz-electronic.de/display/PD/TE0712

Refer to https://wiki.trenz-electronic.de/display/PD/TEM0001 for the current online version of this manual and other available documentation.

The Trenz Electronic TEM0001 is a low cost small-sized FPGA module integrating a Microsemi SmartFusion2 FPGA SoC and 8 MByte Flash memory for configuration and operation.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEM0001-01 block diagram

Main Components

Figure 2: TEM0001-01 FPGA module

  1. Microsemi SmartFusion2 FPGA SoC, U5
  2. 8 Mbyte SDRAM 166MHz, U2
  3. Micro USB2 B socket (receptacle), J9
  4. Switch button (reset), S1
  5. Switch button (user), S2
  6. Red LED (user), D10
  7. Green LED (indicating supply voltage), D1
  8. 8x red LEDs (user), D2 - D9
  9. FTDI USB2 to JTAG/UART interface, U3
  10. 8 Mbyte QSPI Flash memory, U1
  11. 32.768 KHz auxiliary crystal, Y1
  12. 25 MHz main crystal, Y2
  13. 1x14 pin header (2.54mm pitch), J2
  14. 1x6 pin header (2.54mm pitch), J4
  15. 3-pin header (2.54mm pitch), J3
  16. 1x14 pin header (2.54mm pitch), J1
  17. 2x6 Pmod connector, J6

Initial Delivery State

Storage device name



SPI Flash OTP area


SPI Flashempty-


FlashPro identification, should not be changed by customer

Table 1: Initial delivery state of programmable devices on the module

Boot Process

There is are no bootmode selection Microchip SmartFusion2 SoC boots always from internal configuration flash, optionally software code for the Cortex-M or soft CPU can be placed to eNVM.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

BankConnector DesignatorI/O Signal CountBank VoltageNotes
1J11 I/O's3.3V-
1J24 I/O's3.3V2 I/O's of bank 1 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of Bank 7 or pins can be shared.
2J113 I/O's3.3V-
2J25 I/O's3.3V-
2J68 /O's3.3VPmod Connector.
3J45 I/O's3.3VJTAG interface.
4J32 I/O's3.3VI/O's (PROBE A, B) are dedicated to live probes.
7J22 I/O's3.3VThose 2 I/O's are dedicated to pull-up 2 I/O's of bank 1 or pins can be shared.

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

BankVCCIOI/O's CountAvailable on ConnectorsNotes
13.3V1456 I/O's connected to FTDI chip, 1 I/O used for user button S2, 2 I/O's connected to red user LEDs D2 and D10.
23.3V37266 I/O's user for QSPI Flash, 5 I/O's connected to red user LEDs D3 ... D7.
33.3V55Bank 3 is dedicated to JTAG interface.
43.3V2422 I/O's are dedicated to live probes, all other I/O's are used as memory interface.
73.3V2222 I/O's available on header J2, 2 I/O's connected to red user LEDs D8 and D9, all other I/O's are used as memory interface.

Table 3: General overview of FPGA I/O banks

JTAG Interface

JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is implemented with FTDI FT2232H USB2 to JTAG/UART bridge IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

JTAG SignalPin on Header J4Note

can be left open for normal operation

Table 4: optional JTAG header

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:

SD IO Signal Schematic NameFPGA I/OFlash IC U1 PinNote
F_CSBank 2, pin K151QSPI chip select
F_CLKBank 2, pin P186QSPI clock
F_DIBank 2, pin P195QSPI data
F_DOBank 2, pin K162QSPI data
F_D2Bank 2, pin J183QSPI data
F_D3Bank 2, pin N197QSPI data

Table 5: QSPI interface signals

Note: On-board SPI Flash is connected to regular FPGA I/O pins, access to it is only possible when using custom SPI flash IP core or via MSS subsystem SPI when it is connected via fabric to those pins. There is no automatic boot from this flash.

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Winbond Serial Flash Memory W74M64FV with 64 MBit (8 MByte) storage capacity.


The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2.


FTDI FT2232H Channel A works as JTAG interface compatible to Libero tools. Channel B is connected to FPGA pins with direct access to MSS UART peripheral.

The configuration of FTDI FT2232H is pre-programmed to the EEPROM U9 to make it work as FlashPro5 interface for Libero tools.

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Clock SourceSchematic NameFrequencyClock Input Destination
MEMS Oscillator, U7CLK12M12.0000 MHzFTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin N16

Crystal Oscillator, Y1

-32.768 KHzFPGA SoC U5 auxiliary clock, pins W17/Y17
Quartz Crystal Oscillator, Y2-25.000 MHzFPGA SoC U5 main clock, pins W18/Y18

Table 6: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

LEDColorSignal Schematic NameFPGANotes
D1Green--Indicating 3.3V board supply voltage

Table 7: LEDs of the module

Push Buttons

The TEM0001 FPGA module is equipped with two push buttons S1 and S2:

ButtonSignal Schematic NameFPGANotes
S1USER_BTNB19user configurable
S2RESETU17system reset (reconfiguration)

Table 8: Push buttons of the module


All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEM0001 module needs one single power supply of 5.0V nominal.

There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:

Figure 3: Power Distribution Diagram

Power Consumption

FPGADesignTypical Power, 25C ambient
Mircosemi SmartFusion2 FPGA SoC M2S010-VFG400Not configuredTBD*

Table 9: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Technical Specifications

Absolute Maximum Ratings




Reference document

VIN supply voltage (5.0V nominal)




EP53A7HQI / EP53A7LQI datasheet
I/O Input voltage for FPGA I/O bank-0.33.63VMicrosemi datasheet DS0128

Storage Temperature




LED R6C-AL1M2VY/3T datasheet

Table 10: Absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsReference document
VIN supply voltage (5.0V nominal)4.755.25Vsame as USB-VBUS specification
I/O Input voltage for FPGA I/O bank03.45VMicrosemi datasheet DS0128
Operating temperature range0+70


Winbond datasheet W9864G6GT

Table 11: Recommended operating conditions

Please check Microsemi datasheet DS0128 for complete list of absolute maximum and recommended operating ratings for the FPGA device.

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.


Figure 4: Module physical dimensions drawing

Revision History

Hardware Revision History



PCNDocumentation Link


  • First Production Release
 - TEM0001-01

Table 12: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 5: Module hardware revision number

Document Change History




  • fixed typographical and other mistakes

v.33 Antti Lukats
  • change documentation


v.31Ali Naseri
  • initial release

Table 13: Document change history