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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware



Table of contents

Overview

Firmware for PCB-Master CPLD with designator U5: LCMX02-1200HC.

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
200MHZCLK_ENout30 
BUTTONin77Reset Button
CPLD_JTAG_TCK 91not accessible as IO
CPLD_JTAG_TDI 94not accessible as IO
CPLD_JTAG_TDO 95not accessible as IO
CPLD_JTAG_TMS 90not accessible as IO
DDR3_SCL 43/ currently_not_used
DDR3_SDA 42/ currently_not_used
DONEin18FPGA Done
EN_1V8out58Power Enable
EN_3V3FMCout60Power Enable
EN_FMC_VADJout51Power Enable
F1PWMout98 
F1SENSEin99/ currently_not_used
FEX_DIR 19/ currently_not_used
FEX0 out12PERST from PCIe slot
FEX1 15/ currently_not_used
FEX10 4/ currently_not_used
FEX11 10/ currently_not_used
FEX2 13/ currently_not_used
FEX3 9/ currently_not_used
FEX4 3/ currently_not_used
FEX5 7/ currently_not_used
FEX6 24/ currently_not_used
FEX7 17/ currently_not_used
FEX8 21/ currently_not_used
FEX9 25/ currently_not_used
FMC_PG_C2M 69/ currently_not_used
FMC_PG_M2C 68/ currently_not_used
FMC_PRSNT_M2C_L 70/ currently_not_used
FMC_SCL 49/ currently_not_used
FMC_SDA 48/ currently_not_used
FMC_TCK 27/ currently_not_used
FMC_TDI 31/ currently_not_used
FMC_TDO 32/ currently_not_used
FMC_TMS 28/ currently_not_used
FMC_TRST 36/ currently_not_used
FPGA_IIC_OE 14/ currently_not_used
FPGA_IIC_SCL 1/ currently_not_used
FPGA_IIC_SDA 16/ currently_not_used
LED1out76Status LED D1 (green)
LTM_1V_IO0 86Power Good
LTM_1V_IO1 88Power Good
LTM_1V5_4V_IO0 85Power Good
LTM_1V5_4V_IO1 83Power Good
LTM_1V5_RUN 74/ currently_not_used
LTM_4V_RUN 75/ currently_not_used
LTM_SCL 67/ currently_not_used
LTM_SDA 66/ currently_not_used
LTM1_ALERT 65/ currently_not_used
LTM2_ALERT 64/ currently_not_used
PCIE_RSTBin37PERST from PCIe card edge connector
PG_1V8in59Power Good
PG_3V3in61Power Good
PG_FMC_VADJin52Power Good
PLL_SCL 2/ currently_not_used
PLL_SDA 8/ currently_not_used
PROGRAM_Bout20FPGA PROG_B
VID0_FMC_VADJout53FMC EN5365QI power selection pin
VID1_FMC_VADJout54FMC EN5365QI power selection pin
VID2_FMC_VADJout57FMC EN5365QI power selection pin

 

Functional Description

JTAG

CPLD JTAG is always enabled.

Power

Power sequence on will be executed over 4 States:

State machine restart power sequencing, if on of the power good signal are lost.

FMC VADJ is set to 1.8V.

Reset

PROGRAM_B is controlled by push button after power up sequencing is ready.

CLK

200MHz CLK is enabled after power up.

Si5338 configuration is not implemented.

Button

Button is debounced and controls PROG_B signal from FPGA.

LED

LED is used as Status LED for power management and programming. Status depends on blink sequence.

StatusBlink sequenceComment
Error - Power IDLE state********~5,8 Hz,
Error - Power PS1 state*****ooo~0,7 Hz, duty cycle 5/8
Error - Power PS2 state****oooo~0,7 Hz, duty cycle 4/8
Power Ready, FPGA not programmed***ooooo~0,7 Hz, duty cycle 3/8
--**oooooo~0,7 Hz, duty cycle 2/8, currently not used
--*ooooooo~0,7 Hz, duty cycle 1/8, currently not used
Power Ready, FPGa programmedconstant on 

 

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription


REV01REV01


REV01 finished
2017-05-29

v.1

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Initial release
 All  

 

Appx. A: Legal Notices