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Table of Contents


Refer to https://wiki.trenz-electronic.de/display/PD/TE0841+TRM for online version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale FPGA, 1 GByte of DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

Key Features

Additional assembly options for cost or performance optimization plus high volume prices are available on request.

Block Diagram

Figure 1: TE0841-01 block diagram.

Main Components

Figure 2: TE0841-01 main components.

  1. Xilinx Kintex UltraScale FPGA, U1
  2. Ultra performance oscillator @25.000000 MHz, U3
  3. 12A PowerSoC DC-DC converter (0.95V), U14
  4. 12A PowerSoC DC-DC converter (0.95V), U7
  5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11
  6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
  7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
  8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  11. Programmable quad clock generator, U2
  12. 32 MByte QSPI Flash, U6
  13. 4 Gbit DDR4 SDRAM, U4
  14. 4 Gbit DDR4 SDRAM, U5
  15. System Controller CPLD, U18
  16. Low-dropout (LDO) linear regulator (MGTAUX), U9
  17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Initial Delivery State

Storage device name



System Controller CPLDDefault firmware-

Quad SPI Flash OTP area


Not programmed
Quad clock generator OTP areaEmptyNot programmed

Table 1: TE0841-01 module initial delivery state of programmable on-board devices.

Boot Process

By default the configuration mode pins of the FPGA are set to QSPI mode, hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for configuring the QSPI flash memory with the initial FPGA configuration data.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Table below lists bank number, bank type, B2B connection, I/O signal/LVDS pair count and power source for each FPGA PL I/O bank connected to the B2B connectors:

FPGA BankTypeB2B ConnectorI/O Signal CountVoltageNotes
64HRJM148 IOs, 24 LVDS pairsB64_VCCOSupplied by the carrier board
65HRJM18 IOs3.3VOn-module power supply
65HRJM34 IOs, 2 LVDS pairs3.3VOn-module power supply
66HPJM316 IOs, 8 LVDS pairsB66_VCCOSupplied by the carrier board
67HPJM248 IOs, 24 LVDS pairsB67_VCCOSupplied by the carrier board
67HPJM22 IOsB67_VCCOSupplied by the carrier board
68HPJM218 IOs, 9 LVDS pairsB68_VCCOSupplied by the carrier board

Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors.

For detailed information about the pin out, please refer to the Pin-out Tables.

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pin connection information:

LaneBankTypeSignal NameB2B PinFPGA Pin
  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9
  • MGTHRXP0_225, Y2
  • MGTHRXN0_225, Y1
  • MGTHTXP0_225, AA4
  • MGTHTXN0_225, AA3
  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15
  • MGTHRXP1_225, V2
  • MGTHRXN1_225, V1
  • MGTHTXP1_225, W4
  • MGTHTXN1_225, W3
  • MGT_RX2_P
  • MGT_RX2_N
  • MGT_TX2_P
  • MGT_TX2_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21
  • MGTHRXP2_225, T2
  • MGTHRXN2_225, T1
  • MGTHTXP2_225, U4
  • MGTHTXN2_225, U3
  • MGT_RX3_P
  • MGT_RX3_N
  • MGT_TX3_P
  • MGT_TX3_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27
  • MGTHRXP3_225, P2
  • MGTHRXN3_225, P1
  • MGTHTXP3_225, R4
  • MGTHTXN3_225, R3
  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N
  • JM1-12
  • JM1-10
  • JM1-6
  • JM1-4
  • MGTHRXP0_224, AH2
  • MGTHRXN0_224, AH1
  • MGTHTXP0_224, AG4
  • MGTHTXN0_224, AG3
  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N
  • JM1-24
  • JM1-22
  • JM1-18
  • JM1-16
  • MGTHRXP1_224, AF2
  • MGTHRXN1_224, AF1
  • MGTHTXP1_224, AF6
  • MGTHTXN1_224, AF5
  • MGT_RX6_P
  • MGT_RX6_N
  • MGT_TX6_P
  • MGT_TX6_N
  • JM1-27
  • JM1-25
  • JM1-19
  • JM1-17
  • MGTHRXP2_224, AD2
  • MGTHRXN2_224, AD1
  • MGTHTXP2_224, AE4
  • MGTHTXN2_224, AE3
  • MGT_RX7_P
  • MGT_RX7_N
  • MGT_TX7_P
  • MGT_TX7_N
  • JM3-2
  • JM3-4
  • JM3-1
  • JM3-3
  • MGTHRXP3_224, AB2
  • MGTHRXN3_224, AB1
  • MGTHTXP3_224, AC4
  • MGTHTXN3_224, AC3

Table 3: FPGA to B2B connectors routed MGT lanes overview.

Below are listed MGT banks reference clock sources.

Clock signalBankSourceFPGA PinNotes
MGT_CLK0_P225B2B, JM3-33MGTREFCLK0P_225, Y6Supplied by the carrier board.
MGT_CLK1_P225U2, CLK1BMGTREFCLK1P_225, V6On-board Si5338A.
MGT_CLK2_P224B2B, JM3-34MGTREFCLK2P_224, AD6Supplied by the carrier board.
MGT_CLK3_P224U2, CLK2BMGTREFCLK3P_224, AB6On-board Si5338A.

Table 4: MGT banks reference clock sources.

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

JTAG Signal

B2B Connector Pin


Table 5: JTAG interface signals.

JTAGMODE pin 89 in B2B connector JM1 should be set low or grounded for normal operation. Set this high for SC CPLD update vie JTAG interface.

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
JTAGMODEInputJTAG selectLow for normal operation.
NRST_SC0InputReset -
SC1--Not used by default.
SC2--Not used by default.
SC3--Not used by default.
SC4--Not used by default.

Table 6: System Controller CPLD I/O pins.

Quad SPI Interface

Quad SPI interface is connected to the FPGA configuration bank 0.

Signal NameQSPI Flash Memory U6 PinFPGA Pin
SPI_D1D2D01_DIN_0, Y7
SPI_D2C4D02_0, U7
SPI_D3D4D03_0, V7

Table 7: Quad SPI interface signals and connections.

I2C Interface

There are two PL bank 65 I/O pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.

Additionally, two PL bank 65 I/O pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary I/Os.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U18) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

DDR Memory

By default TE0841 module has two NT5AD256M16 DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Programmable Clock Genetraor

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate several reference clocks for the module.

Si5338A Pin
Signal Name / Description
Connected ToDirectionNote



Not connected.Input

Not used.

IN2-GNDInputNot used.


Reference input clock.

U3, pin 3Input25.000000 MHz oscillator, Si8208AI.


-GNDInputI2C slave device address LSB.



Not connected.InputNot used.
IN6-GNDInputNot used.



U1, R23Output

FPGA bank 45.

CLK0BCLK1_NU1, P23Output
CLK1AMGT_CLK1_NU1, V5OutputFPGA MGT bank 225 reference clock.
CLK2AMGT_CLK3_NU1, AB5OutputFPGA MGT bank 224 reference clock.


U1, pin T24Output

FPGA bank 45.

CLK3BCLK0_NU1, pin T25Output

Table 8: Programmable quad PLL clock generator inputs and outputs.


The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock SourceFrequencySignal NameClock Destination
U3, SiT8208AI25.000000 MHzCLKU2, pin 3 (IN3)
U11, DSC1123DL5200.0000 MHzCLK200M_PU1, pin R25
CLK200M_NU1, pin R26
B2B, JM3-31UserMGT_CLK0_NU1, pin Y5
B2B, JM3-33MGT_CLK0_PU1, pin Y6
B2B, JM3-32UserMGT_CLK2_NU1, pin AD5
B2B, JM3-34MGT_CLK2_PU1, pin AD6

Table 9: Reference clock signals.

On-board LEDs

LEDColorConnected toDescription and Notes
D1GreenSystem Controller CPLD, bank 3Exact function is defined by SC CPLD firmware.

Table 10: On-board LEDs.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current

Table 11: Typical power consumption.


* TBD - To Be Determined.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any SoC's I/O bank voltages (B64_VCO, B65_VCO, B66_VCO and B67_VCO). All I/Os should be tri-stated during power-on sequence.

Power-On Sequence

For the highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously. It is important that all I/Os of the carrier board are 3-stated at the beginning of the power-on cycle until 3.3V is present on B2B connector JM2 pins 10 and 12, indicating that all on-module PL supply voltages have become stable and Zynq MPSoC module is powered up properly.

Figure 3: TE0841-01 Power-on sequence.

See also Xilinx datasheet DS892 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0841 module.

Power Rails

Power Rail Name

B2B JM1 Pins

B2B JM2 Pins


VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
B64_VCO9, 11-InputHR (High Range) bank voltage.
B66_VCO-1, 3InputHP (High Performance) bank voltage.
B67_VCO-7, 9InputHP (High Performance) bank voltage.
B68_VCO-5InputHP (High Performance) bank voltage.


79-InputRTC battery supply voltage.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage level.

Table 12: Module power rails.

Board to Board Connectors

Variants Currently In Production

Module Variant


Temperature Range

Table 13: Module variants in production.

Technical Specifications

Absolute Maximum Ratings




Reference Document

VIN supply voltage



EN63A0QI, TPS74401RGW datasheets.
3.3VIN supply voltage-0.13.75VTPS27082, LCMXO2-256HC datasheets.
Supply voltage for HR I/O banks (VCCO)
VXilinx datasheet DS892.
Supply voltage for HP I/O banks (VCCO)
2.000VXilinx datasheet DS892.
I/O input voltage for HR I/O banks
VCCO + 0.550
VXilinx datasheet DS892.
I/O input voltage for HP I/O banks
VCCO + 0.550
VXilinx datasheet DS892.
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)-0.5001.320VXilinx datasheet DS892.
GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage
VXilinx datasheet DS892.

Storage temperature





Table 14: Module absolute maximum ratings.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage3.35.5VTPS82085SIL, TPS74401RGW datasheet
3.3VIN supply voltage2.3753.6VLCMXO2-256HC datasheet
Supply voltage for HR I/O banks (VCCO)1.140
VXilinx datasheet DS892
Supply voltage for HP I/O banks (VCCO)
VXilinx datasheet DS892
I/O input voltage
VCCO + 0.20VXilinx datasheet DS892

Table 15: Module recommended operating conditions.


Assembly variants for higher storage temperature range are available on request.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

All dimensions are given in millimeters.

Figure 4: Module physical dimensions.

Revision History

Hardware Revision History



PCNDocumentation Link


First production revision


Table 16: Hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 5: Module hardware revision number.

Document Change History





Jan Kumann, Ali Naseri
Initial document.

Table 17: Document change history.