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Table of Contents


The Trenz Electronic TEI0001 MAX1000 is a low cost small-sized FPGA module integrating a Intel MAX 10 FPGA SoC, 8 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.

Use short link the Wiki Ressource page: for example:
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects
Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

  1. Intel MAX 10 10M08 FPGA SoC, U1
  2. 8 Mbyte SDRAM 166MHz, U2
  3. 8 Mbyte QSPI Flash memory, U5
  4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
  5. FTDI USB2 to JTAG/UART adapter, U3
  6. Configuration EEPROM for FTDI chip, U9
  7. 12.0000 MHz oscillator, U7
  8. 8x red user LEDs, D2 ... D9
  9. Red LED (Conf. DONE), D10
  10. Green LED (indicating supply voltage), D1
  11. Push button (user), S2
  12. Push button (reset), S1
  13. Micro USB2 B socket (receptacle), J9
  14. 1x14 pin header (2.54mm pitch), J2
  15. 1x6 pin header (2.54mm pitch), J4
  16. 2x6 Pmod connector, J6
  17. 3-pin header (2.54mm pitch), J3
  18. 1x14 pin header (2.54mm pitch), J1

Initial Delivery State

Storage device name



Quad SPI Flash, U5

DEMO Design

I2C Configuration EEPROM, U9



Table 1: Initial delivery state of programmable devices on the module

Boot Process

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

BankConnector DesignatorI/O Signal CountBank VoltageNotes
2J14 I/O's3.3V-
J68 I/O'sPmod connector
5J12 I/O's3.3V-
J29 I/O's2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors)
1AJ17x analog inputs or GPIO's, 1x Analog reference voltage (AREF)3.3Vanalog pins usable as GPIO's as alternative function

J31x analog inputs or GPIO, 1x dedicated analog input
1BJ4JTAG interface and 'JTAGEN' signal (5 I/O's)3.3VJTAG enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

BankI/O's CountConnected toNotes
241x14 pin header, J1user GPIO's
8Pmod connector, J6user GPIO's
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6oscillator not fitted, footprints available for Microchip MEMS oscillator
591x14 pin header, J22 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6188 MByte SDRAM 166MHz, U216bit SDRAM memory interface
3228 MByte SDRAM 166MHz, U216bit SDRAM memory interface
6LIS3DH 3-axis accelerometer, U44 I/O's for SPI interface, 2 interrupt lines
1A81x14 pin headers J17 analog inputs or GPIO's, 1 pin analog reference voltage input
2pin headers J11 analog inputs or GPIO, 1 dedicated analog input
1B5pin header J44 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
88LEDs D2 ... D9Red user LEDs
6QSPI Flash memory, U56 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization
6FTDI FT2232H JTAG/UART Adapter, U36 pins configurable as GPIO/UART or other serial interfaces
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
1User button S2user configurable
1Reset button S1 and pin J2-10low active reset line for FPGA reconfiguration

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:

JTAG SignalPin on Header J4Note
JTAGEN2leave floating when use JTAG interface, otherwise signals on FPGA are GPIOs

Table 4: optional JTAG pin header

On-board Peripherals

Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Winbond W74M64FVSSIQ with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via SPI interface.

Serial Memory U5 PinSignal Schematic NameConnected toNotes
Pin 1, CSF_CSFPGA bank 8, pin B3
chip select
Pin 6, CLKF_CLKFPGA bank 8, pin A3clock
Pin 5, SI/IO0F_DIFPGA bank 8, pin A2data in / out

FPGA bank 8, pin C4

data in / out, configuration dual-purpose pin of FPGA
Pin 3, WP/IO2DEVCLRNFPGA bank 8, pin B9data in / out, configuration dual-purpose pin of FPGA
Pin 2, SO/IO1F_DOFPGA bank 8, pin B2data in / out

Table 5: Quad SPI Flash memory interface


The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

Data input/output

DQ0 ... DQ15

bank 6

Data mask

DQM0 ... DQM1

bank 6

ClockCLKbank 3
Control Signals


bank 3

Chip select


bank 3

Clock enable


bank 3

Row Address Strobe


bank 3

Column Address Strobe

WEbank 3Write Enable

Table 6: 16bit SDRAM memory interface

FTDI FT2232H Chip

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0TCKFPGA bank 1B, pin G2
JTAG interface
Pin 13, ADBUS1TDIFPGA bank 1B, pin F5
Pin 14, ADBUS2TDOFPGA bank 1B, pin F6

FPGA bank 1B, pin G1

Pin 32, BDBUS0BDBUS0FPGA bank 8, pin A4user configurable
Pin 33, BDBUS1BDBUS1FPGA bank 8, pin B4
user configurable
Pin 34, BDBUS2BDBUS2FPGA bank 8, pin B5user configurable
Pin 35, BDBUS3BDBUS3FPGA bank 8, pin A6user configurable
Pin 37, BDBUS4BDBUS4FPGA bank 8, pin B6
user configurable
Pin 38, BDBUS5BDBUS5FPGA bank 8, pin A7user configurable

Table 7: FTDI chip interfaces and pins

3-Axis Accelerometer

On the TEI0001 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

Accelerometer U4 PinSignal Schematic NameConnected toNotes
Pin 11, INT1SEN_INT1FPGA bank 3, pin J5
Interrupt lines
Pin 9, INT2SEN_INT2FPGA bank 3, pin L4
Pin 6, SDA/SDI/SDOSEN_SDIFPGA bank 3, pin J7SPI interface


FPGA bank 3, pin K5

Pin 4, SCL/SPCSEN_SPCFPGA bank 3, pin J6
Pin 8, CSSEN_CSFPGA bank 3, pin L5
Pin 13, ADC3ADC35VSense 5V input voltage

Table 8: 3-axis accelerometer interfaces and pins

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Clock SourceSchematic NameFrequencyClock Input Destination
Microchip MEMS Oscillator, U7CLK12M12.0000 MHzFTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin H6
optional Microchip MEMS Oscillator, U6 (not fitted)CLK_X-FPGA SoC bank 2, pin G5

Table 9: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

LEDColorSignal Schematic NameFPGANotes
D1Green--Indicating 3.3V board supply voltage
D2Red'LED1'bank 8, pin A8user
D3Red'LED2'bank 8, pin A9user
D4Red'LED3'bank 8, pin A11user
D5Red'LED4'bank 8, pin A10user
D6Red'LED5'bank 8, pin B10user
D7Red'LED6'bank 8, pin C9user
D8Red'LED7'bank 8, pin C10user
D9Red'LED8'bank 8, pin D8user
D10Red'CONF_DONE'bank 8, pin C5indication configuration is DONE when LED is off

Table 10: LEDs of the module

Push Buttons

The FPGA module is equipped with two push buttons S1 and S2:

ButtonSignal Schematic NameFPGANotes
S1'USER_BTN'bank 8, pin E6user configurable
S2'RESET'bank 8, pin E7FPGA reset

Table 11: Push buttons of the module


All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEI0001 module needs one single power supply of 5.0V nominal.

There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:

Power Consumption

FPGADesignTypical Power, 25C ambient
Intel MAX 10 10M08 FPGA SoCNot configuredTBD*

Table 12: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Power Rails

Connector DesignatorVCC / VCCIO Schematic NameVoltageDirectionPinsNotes
J25V5.0VOutPin 14-
VIN5.0VInPin 13-
3.3V3.3VOutPin 12-



OutPin 6, 12-


5.0VInPin 1-

Table 13: Connector power pin description

Bank Voltages



Voltage Range

23.3Vall bank voltages fixed

Table 14: FPGA SoC VCCO bank voltages

Technical Specifications

Absolute Maximum Ratings




Reference document

VIN supply voltage (5.0V nominal)




EP53A7HQI datasheet
I/O Input voltage for FPGA I/O bank-0.54.12VIntel MAX 10 datasheet

Storage Temperature




LED R6C-AL1M2VY/3T datasheet

Table 15: Absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsReference document
VIN supply voltage (5.0V nominal)4.755.25Vsame as USB-VBUS specification
I/O Input voltage for FPGA I/O bank–0.53.6VIntel MAX 10 datasheet
Operating temperature range0+70


Winbond datasheet W9864G6GT

Table 16: Recommended operating conditions

Please check Intel MAX 10 datasheet  for complete list of absolute maximum and recommended operating ratings for the FPGA device.

Physical Dimensions



Revision History

Hardware Revision History



PCNDocumentation Link
-03Current available revision-TEI0001-03


First Production Release


Table 17: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History




Ali Naseri
  • small corrections



Ali Naseri

  • First TRM release

Table 18: Document change history