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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware


Table of contents

Overview

CPLD Device with designator U21: LCMX02-256HC

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
C_TCK     in30JTAG B2B
C_TDI     in32JTAG B2B
C_TDO     out1JTAG B2B
C_TMS     in29JTAG B2B
EN1       in27Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback
ERR_OUT   in4PS_ERROR_OUT, see ug1085
ERR_STATUSin5PS_ERROR_STATUS, see ug1085 / currently_not_used
JTAGEN    in26Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
MODE      in25Boot Mode for Zynq/ZynqMP Devices (Flash or SD)
MODE0     out12ZynqMP Boot Mode Pin 0
MODE1     out13ZynqMP Boot Mode Pin 1
MODE2     out14ZynqMP Boot Mode Pin 2
MODE3     out16ZynqMP Boot Mode Pin  3
NOSEQ     inout23/ currently_not_used
PGOOD     out28Module Power Good.
PHY_LED1  in17ETH PHY LED1
TCK     out9JTAG ZynqMP
TDI       out8JTAG ZynqMP
TDO       in10JTAG ZynqMP
TMS       out11JTAG ZynqMP
X0        out20FPGA IO / Firmware Variant
X1        out21FPGA IO / PHY_LED1

 

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.

Boot Mode

2 Boot Modes can be selected via B2B Pin Mode. For other options Firmware update is necessary. Trenz Electronic provides currently 2 Firmware variants, one for SD and one for QSPI usage.

ModeQSPI-VariantSD-Variant
ZeroJTAGBoot from SD
OneBoot from FlashJTAG

For other UltraScale+ Boot Modes options custom firmware is needed, see also Table 11.1 Boot Modes from Xilinx UG1085.

Set Boot Mode to JTAG, to write boot image to QSPI with Xilinx tools (Vivado or SDK).

Power

PGOOD is EN1 and not ER_OUT. There is no additional power management controlled by CPLD.

Internal pullup is used for detection, ER_OUT IO powered by 1.8V. To detect power status, also B2B 1.8V or 3.3V output is usable.

X0/X1 Pin

PinDescription
X0Firmware Variant: 0 SD boot, 1: QSPI
X1PHY_LED1

Appx. A: Change History

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription


REV02REV02, REV01

 

  • update description - PHY LED correction
2017-08-21v.9REV02REV02, REV01John Hartfiel
  • Revision 02 finished
  • small text updates
2017-08-17v.8REV02REV02, REV01John Hartfiel
  • Revision 02 working in process
  • Boot Mode
  • X1 output
2017-06-08v.4REV01REV01John Hartfiel
  • document style update
2017-03-06v.2REV01REV01John Hartfiel
  • Revision 01 finished
2017-03-06

v.1

REV01REV01


  • Initial release
 All  

 

Appx. B: Legal Notices