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Overview

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The Trenz Electronic TEF0008 is a FPGA to Mezzanine Card (FMC) based on VITA 57.1 FMC HPC Standard, with four SFP+ 10Gb fiber optical (850nm) ports. It is inteded for use on a FMC HPC carrier and can not be used stand-alone.

Key Features

• Four SFP+ 10Gb (850nm) ports
• HPC FMC connector
• Low jitter programmable clock generator
• Intel(Altera) Max10 FPGA 10M08SAU169C8G
• Status LED (green)

Block Diagram

Figure 1: TEF0008-01 block diagram.

Main Components

Figure 2: TEF0008-01 FMC overview.

Table 1: TEF0008-01 main components.

1. MAX10 FPGA, U5
2. Programmable low jitter clock generator Si5354A, U2
3. Status LED (green), D1
4. 3.3V to 1.8V DCDC converter, U6
5. Quad SFP+ cage and connectors, J4-J7
6. 1x6 pin header for JTAG programming of FPGA (3.3V), J3
7. 1x3 pin header for I²C (1.8V), J1
8. XTAL 54.0000 MHz (CX3225SB), Y1
9. Oszillator 25.000000 MHz (SiT8008B), U1
10. HPC FMC connector, J2
11. 128KBit EEPROM, U4
12. Testpoints Max10, TP7-TP9
13. Testpoints JTAG, TP1-TP4
14. Testpoints Power, TP5, TP6, TP10

Initial Delivery State

Table 2: Initial delivery state of programmable devices on the module.

Boot Process

The MAX10 FPGA boots form its internal configuration flash memory, which is programmable via JTAG.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the FPGA I/O bank and B2B connector: 

Table 3: General overview of I/O signals connected to the B2B connectors.

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MGT Lanes

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TD/RD) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, and HPC FMC Pin:

Table 4: MGT lanes.

Below are listed MGT banks reference clock sources.

Table 5: MGT reference clock sources.

SFP+ Control Interface

Follwowing table contains a brief description of the control and status signals of the SFP+ connectors:

JTAG Interface

JTAG access to the MAX10 FPGA is provided through HPC FMC Connector and an additional pin header connector as well as testpoints.

Table 6: JTAG interface signals.

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I²C Interface

On-board I²C devices are connected to the HPC FMC Pin C30 SCL and pin C31 SDA which are reserved for I²C. Level shift and for PLL and SFP+ I²C is done by the FPGA as well as MUX for SFP+. Addresses for on-board devices are listed in the table below:

Table 7: I²C slave device addresses.

On-board Peripherals

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Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator on-board (Si5345A, U2) to generate reference clocks for the module.

Not connected.

 Table 8: Programmable clock generator inputs and outputs.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table 9: Reference clock signals.

EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

On-board LEDs

Table 10: On-board LEDs.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module depends on the design running on the FPGA.

Table 11: Typical power consumption.

 * TBD - To Be Determined with reference design setup.

Power Distribution Dependencies

Regulator dependencies and max. current.

Figure 3: Module power distribution diagram.

Power Rails

Table 12: Module power rails.

Bank Voltages

Table 13: Module PL I/O bank voltages.

Variants Currently In Production

Table 14: Module variants.

Technical Specifications

Absolute Maximum Ratings

Table 15: Module absolute maximum ratings.

Recommended Operating Conditions

Table 16: Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Physical Dimensions

• Module size: 69 mm × 84 mm, SFP+ conector excluded (+ 5.5 mm). See Vita 57.1 standard.

• PCB thickness: 1.6 mm.

• Highest part on PCB top is 9.5 mm (SFP+ cage, excluded front plate),  bottom 1.4 mm (MAX10 FPGA). Please download the step model for exact numbers.

All dimensions are given in millimeters.

Figure 4: Module physical dimensions drawing

Revision History

Hardware Revision History

Table 17: Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure 5: Module hardware revision number.

Document Change History

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Date	Revision	Contributors	Description
		Author Name	What changed?
		Martin Rohrmüller	Initial document.
	all	Jan Kumann, John Hartfiel

Table 18: Document change history.

Disclaimer

02 Sept 2017