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Table of Contents |
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Refer to https://wiki.trenz-electronic.de/display/PD/<name> for the current online version of this manual and other available documentation. |
The Trenz Electronic TEM0002-01 SmartBerry with Raspberry Pi form factor, is an industrial-grade module based on Microsemi SmartFusion2 SoC (System on a Chip). The Module has 128MB DDR3 SDRAM, a Gigabit Ethernet PHY, four PMODs, a GPIO Pin header compatible to the Raspberry Pi pinout and a Micro USB to UART interface. SmartFusion2 combiens a 166 MHz Cortex-M3 core with 256 KByte Flash, 80 KByte SRAM and a 12 kLUT FPGA Core Logic.
Additional assembly options are available for cost or performance optimization upon request.
Figure 1: TEM0002-01 block diagram.
Table 1: TEM0002-01 main components.
Storage device name | Content | Notes |
---|---|---|
Microsemi SmartFusion2 SoC FPGA, U2 | Demo Design | - |
EEPROM, U6 | Programmed | FTDI (FT2232H) configuration data. |
Table 1: Initial delivery state of programmable devices on the module.
The SmartBerry supports
<!-- Connections and Interfaces or B2B Pin's which are accessible by User --> |
I/O signals connected to the SoCs I/O bank and B2B connector:
Bank | Type | B2B Connector | I/O Signal Count | Bank Voltage | Notes |
---|---|---|---|---|---|
64 | HR | JM1 | 8 I/Os | 3.3V | On-module power supply. |
66 | HP | JM3 | 16 I/Os, 8 LVDS pairs | B66_VCCO | Supplied by the carrier board. |
Table x: General overview of PL I/O signals connected to the B2B connectors.
All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.
For detailed information about the pin out, please refer to the Pin-out Tables.
The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.
<!-- TO-DO (future): If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module. --> |
<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. --> |
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
---|---|---|---|---|---|
0 | 225 | GTH |
|
|
|
Table x: MGT lanes.
JTAG access to the ... is provided through B2B connector ....
JTAG Signal | B2B Connector Pin |
---|---|
TCK | JMx-xx |
TDI | JMx-xx |
TDO | JMx-xx |
TMS | JMx-xx |
Table 5: JTAG interface signals.
FPGA / SoC Pin | Connected To | Signal Name | Notes |
---|---|---|---|
MIO0 | J10-9 | SD_CD | Card detect switch |
MIO10 | J10-7 | SD_D0 | |
MIO11 | J10-3 | SD_D1 | |
MIO12 | J10-5 | SD_D2 | |
MIO13 | J10-8 | SD_CMD | |
MIO14 | J10-1 | SD_CLK | |
MIO15 | J10-2 | CD/DAT3 |
Table x: SD Card interface signals and connections.
On board Gigabit Ethernet PHY is provided with ...
Ethernet PHY connection
PHY Pin | PS | PL | B2B | Notes |
---|---|---|---|---|
Table x: ...
On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:
I2C Device | I2C Address | Notes |
---|---|---|
Table x: I2C slave device addresses.
<!-- Components on the Module, like Flash, PLL, PHY... --> |
TEM0002 has 1Gb industrial grade DDR3 SDRAM (U5) in a 16-bit wide memory bus providing total of 128 MBytes of on-board RAM.
The Datasheet notes 800 MHz clocking resulting in 1600 Mb/s data rate and timing specification of 11-11-11 (CL-TRCD-TRP).
On-board Gigabit Ethernet PHY (J2) is provided by Microsemi VSC8531 chip (U1). The Ethernet PHY RGMII interface is connected to Bank 6 of the Microsemi SOC. I/O voltage is fixed at 1.5V. The reference clock input of the PHY is supplied from an external 25.000000 MHz oscillator (U11).
The module has following reference clock signals provided by on-board oscillators:
Clock Source | Schematic Name | Frequency | Clock Destination |
---|---|---|---|
Crystal CX3225CA25000D0HSSCC | Y1 | 25.000 MHz | SmartFusion2 SoC U2 Main XTAL |
Crystal ECX-31B | Y2 | 32.768 KHz | SmartFusion2 SoC U2 AUX XTAL |
SiTime SiT8008AI oscillator | U11 | 25.000000 MHz | Gb Ethernet Copper PHY U1A |
SiTime SiT8008AI oscillator | U14 | 25.000000 MHz | SmartFusion2 SoC U2-Y12 Bank 4 |
Table : Reference clock signals.
In REV02, Y1 will be replaced by a 12MHz crystal.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Red | U2-G16 Bank 1 | |
D2 | Green | U2-G17 Bank 1 | |
D3 | RGB | U2-H5 Bank 7, U2-F6 Bank 7, U2-H6 Bank 7 | |
J2 | Green, Yellow | U2-Y10 Bank 4, U2-U12 Bank 4 | Ethernet: LED1A, LED1B |
J2 | Green, Yellow | U2-V14 Bank 4, U2-U14 Bank 4 | Ethernet: LED2A, LED2B |
Table : On-board LEDs.
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The maximum power consumption of a module mainly depends on the design running on the FPGA.
Power Input | Typical Current |
---|---|
VIN | TBD* |
3.3VIN | TBD* |
Table : Typical power consumption.
* TBD - To Be Determined soon with reference design setup.
Power supply with minimum current capability of ...A for system startup is recommended.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
Regulator dependencies and max. current.
Put power distribution diagram here...
Figure : Module power distribution diagram.
See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.
The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
Put power-on diagram here...
Figure : Module power-on diagram.
If the module has one, describe it here...
NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.
Power Rail Name | B2B JM1 Pins | B2B JM2 Pins | Direction | Notes |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Main supply voltage from the carrier board. |
3.3V | - | 10, 12, 91 | Output | Module on-board 3.3V voltage supply. (would be good to add max. current allowed here if possible) |
B64_VCO | 9, 11 | - | Input | HR (High Range) bank voltage supply from the carrier board. |
VBAT_IN | 79 | - | Input | RTC battery supply voltage from the carrier board. |
... | ... | ... | ... | ... |
Table : Module power rails.
Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered). |
Bank | Schematic Name | Voltage | Voltage Range |
---|---|---|---|
500 (MIO0) | PS_1.8V | 1.8V | - |
501 (MIO1) | PS_1.8V | 1.8V | - |
502 (DDR3) | 1.35V | 1.35V | - |
12 HR | VCCIO_12 | User | HR: 1.2V to 3.3V |
13 HR | VCCIO_13 | User | HR: 1.2V to 3.3V |
33 HP | VCCIO_33 | User | HP: 1.2V to 1.8V |
34 HP | VCCIO_34 | User | HP: 1.2V to 1.8V |
35 HP | VCCIO_35 | User | HP: 1.2V to 1.8V |
Table : Module PL I/O bank voltages.
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NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.
Module Variant | FPGA / SoC | Operating Temperature | Temperature Range |
---|---|---|---|
TE0710-02-35-2CF | XC7A35T-2CSG324C | 0°C to +70°C | Commercial |
TE0715-04-30-3E | XC7Z030-3SBG485E | 0°C to +85°C | Extended |
TE0841-01-035-1I | XCKU035-1SFVA784I | –40°C to +85°C | Industrial |
.. | .. | .. | .. |
Table : Module variants.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | V | - | ||
Storage temperature | °C | - |
Table : Module absolute maximum ratings.
Assembly variants for higher storage temperature range are available on request. |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | ||||
Operating temperature |
Table : Module recommended operating conditions.
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings. |
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 85 mm × 56 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.55 mm.
Highest part on PCB: top approx. 13.3 mm (Ethernet), bottom 1.57mm (SD-Card)Please download the step model for exact numbers.
All dimensions are given in millimeters.
Figure : Module physical dimensions drawing.
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
- | 01 | Prototypes |
Table : Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Put picture of actual PCB showing model and hardware revision number here...
Figure : Module hardware revision number.
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Date | Revision | Contributors | Description |
---|---|---|---|
John Hartfiel | Remove Link to Download | ||
2017-05-30 | v.1 | Jan Kumann | Initial document. |
all | Jan Kumann, John Hartfiel |
Table : Document change history.