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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/IP/Trenz+Electronic+IP+Cores |
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This Trenz Electronic teCORE IP provides a RGPIO (Remote GPIO) Interface to talk to external RGPIO Devices over 3 wire
IP can be used as Master communicate with external RGPIO devices with Slave interface or as Slave communicate with external RGPIO devices with Master interface
This Trenz Electronic teCORE is licensed under MIT License. This IP is included in various Reference Designs or contact Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-IP-Core Request]" to order this IP-Core.
Maximum RGPIO output CLK depends on Master and Slave device implementation. In the most cases maximum frequency of 25MHz is allowed.
Port Name | IO | Description |
---|---|---|
RGPIO_M_CLK | out | RGPIO Master Clock |
RGPIO_M_RX | in | RGPIO Master RXD |
RGPIO_M_TX | out | RGPIO Master TXD |
Port Name | IO | Description |
---|---|---|
RGPIO_S_CLK | out | RGPIO Slave Clock |
RGPIO_S_RX | in | RGPIO Slave RXD |
RGPIO_S_TX | out | RGPIO Slave TXD |
Port Name | IO | Description |
---|---|---|
RGPIO_M_OUT | out | Data output to slave device |
RGPIO_M_IN | in | Data input from slave device |
RGPIO_M_RESERVED_OUT | out | Reserved for future usage |
RGPIO_M_RESERVED_IN | in | Reserved for future usage |
RGPIO_M_SLAVE_ACTIVATION_CODE | out | Activation code from external slave for information only |
RGPIO_M_ENABLE | in | Enable RGPIO communication |
RGPIO_M_USRCLK | in | RGPIO transmission CLK for master and slave |
RGPIO_M_RESET_N | in | RGPIO Reset |
Port Name | IO | Description |
---|---|---|
RGPIO_S_OUT | out | Data output to master device |
RGPIO_S_IN | in | Data input from master device |
RGPIO_S_RESERVED_OUT | out | Reserved for future usage |
RGPIO_S_RESERVED_IN | in | Reserved for future usage |
RGPIO_S_MASTER_ACTIVATION_CODE | out | Activation code from external master for information only |
RGPIO_S_ENABLED | out | Interface status |
This chapter includes guidelines and additional information to facilitate designing with the core.
This chapter describes customizing and generating the core, constraining the core, and the simulation, synthesis and implementation steps that are specific to this IP core. More detailed information about the standard Vivado® design flows and the Vivado IP integrator can be found in the following Vivado Design Suite user guides:
This section includes information about using Xilinx® tools to customize and generate the core in the Vivado Design Suite.
This section contains information about constraining the core in the Vivado Design Suite.
This section is not applicable for this IP core.
This section is not applicable for this IP core.
This section is not applicable for this IP core.
Maximum RGPIO output CLK depends on Master and Slave device implementation. In the most cases maximum frequency of 25MHz is allowed.
This section is not applicable for this IP core.
This section is not applicable for this IP core.
This section is not applicable for this IP core.
This section is not applicable for this IP core.
This core does not support simulation.
This section contains information about synthesis and implementation in the Vivado Design Suite. For details about synthesis and implementation, see the Vivado Design Suite User Guide:
There is no example Design for this IP core release.
There is no test bench for this IP core release.
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