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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware



Table of contents

Overview

Firmware for PCB CPLD with designator U7. CPLD Device in Chain: LCMX02-256HC

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
C_LED / LED1 out17 LED D4
DONEin28FPGA Done signal
F_TCK / C_TCKout9FPGA JTAG
F_TDI / C_TDIout21FPGA JTAG
F_TDO / C_TDOin5FPGA JTAG
F_TMS / C_TMSout4FPGA JTAG
GND
10GND
GND
11GND
GND
12GND
GND
13GND
GND
14connected to GND
JTAGMODE
26Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
MODE
16/ currently_not_used
PG_ALLin27Power sense from 1.8V/3.3V
PGOOD
25/ currently_not_used
PROG_Bout23FPGA Prog_B
RESINin8external reset from B2B
TCK / M_TCKin30B2B JTAG
TDI / M_TDIin32B2B JTAG
TDO / M_TDOout1B2B JTAG
TMS / M_TMSin29B2B JTAG
XIOout20FPGA IO from Bank14 H26 / 24.18MHz CLK from CPLD internal Osc.

 

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.

Reset

PROG_B is RESIN and PG_ALL.

Power

PG_ALL is used for PROG_B Reset  and LED.

LED

LED D4

StatusConditionDescription
ONRESIN=0external Reset is set
fast blinkPG_ALL=0PG_ALL Problem (1.8V)
slow blinkDONE=0FPGA not programmed
very slow blink
ready


Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription


 

 REV01 REV02,REV03


Revision 01, release date 2014-07-02
2017-06-07

v.1

 REV01 REV02,REV03


Initial release
 All  

 

Legal Notices