Template Revision 2.2 - on construction

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Important General Note:

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Table of Contents

Overview

Notes :

The Trenz Electronic TEI0010 AnalogMax is a low cost small-sized FPGA module integrating an Intel MAX 10 FPGA SoC, 8 MByte serial memory for configuration and operation and 8 MByte SDRAM. The board is equipped with several sensors for analog values like a 3-axis accelerometer, temperature sensor, smoke detector and a 8-channel 12bit ADC/DAC.

Refer to http://trenz.org/analogmax-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • List of key features of the PCB

Block Diagram

Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


  1. Intel MAX 10 10M08 FPGA SoC, U1
  2. 8 Mbyte SDRAM 166MHz, U2
  3. LT LTC1799 oscillator, U10
  4. Analog Devices ADXL362BCCZ MEMS 3-axis accelerometer, U11
  5. Analog Devices ADT7320UCPZ temperature sensor, U8
  6. Analog Devices ADPD188BI smoke detector, U14
  7. Winbond W74M64FV QSPI Flash memory, U5
  8. Analog Devices AD5592RBCPZ ADC/DAC, U12
  9. 12.0000 MHz MEMS oscillator, U7
  10. FTDI USB2 to JTAG/UART adapter, U3
  11. Push button (reset), S1
  12. Micro USB2 B socket (receptacle), J9
  13. Configuration EEPROM for FTDI chip, U9
  14. Push button (user), S2
  15. 8x red user LEDs, D2 ... D9
  16. Red LED (Conf. DONE), D10
  17. Green LED (indicating 3.3V supply voltage), D1
  18. 3-pin header (2.54mm pitch), J3
  19. 1x14 pin header (2.54mm pitch), J1
  20. 1x6 pin header (2.54mm pitch), J4
  21. 1x14 pin header (2.54mm pitch), J2
  22. 2x6 Pmod connector, J6

Initial Delivery State

Storage device name

Content

Notes

Quad SPI Flash, U5

DEMO Design

-
FTDI chip configuration EEPROM, U9Programmed-

Control Signals

  • Overview of Boot Mode, Reset, Enables,

To get started with TEI0010 board, some basic signals are essential and are described in the following table:

Control signal

Switch / Button / LED / PinSignal Schematic Names

Connected to

Functionality

Notes
MAX10 FPGA U1 JTAGENheader J4, pin 2JTAGENMAX10 FPGA U1, bank 1B, pin E5high: MAX 10 JTAG enabled,
floating: MAX 10 JTAG disabled		switch the JTAG pins to user GPIO's if drive this pin to GND
MAX10 FPGA U1 Resetheader J2, pin 10RESETMAX10 FPGA U1, bank 8, pin E7low active reset linealso connected to Reset push button S1
Supply voltage indicatorGreen LED D13.3VDCDC U4indicating 3.3V voltage level-
Configuration DONE indicatorRed LED D10CONF_DONEMAX10 FPGA U1, bank 8, pin C5indicating FPGA configuration completedON: configuration completed, OFF: FPGA not configured
Reset Push buttonS1RESETMAX10 FPGA U1, bank 8, pin E7low active logic-
User Push buttonS2USER_BTNMAX10 FPGA U1, bank 8, pin E6low active logicavailable to user


Boot Process

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

BankConnector DesignatorI/O Signal CountBank VoltageNotes
2J14 I/O's3.3V-
J68 I/O'sPmod connector
5J12 I/O's3.3V-
J29 I/O's2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors)
1BJ4JTAG interface and 'JTAGEN' signal (5 I/O's)3.3VJTAG enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions
J31 I/O-

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

BankI/O's CountConnected toNotes
241x14 pin header, J1user GPIO's
8Pmod connector, J6user GPIO's
1clock oscillator, U712.0000 MHz reference clock input
1reference clock oscillator, U10reference clock input from oscillator U10
1accelerometer IC, U11interrupt 1 line of Analog Devices MEMS accelerometer
591x14 pin header, J22 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
1accelerometer IC, U11interrupt 2 line of Analog Devices MEMS accelerometer
1reference clock oscillator, U10oscillator adjustable with three steps of clock output
1temperature sensor IC, U8interrupt line of temperature thresholds
6188 MByte SDRAM 166MHz, U216bit SDRAM memory interface
3228 MByte SDRAM 166MHz, U216bit SDRAM memory interface
3SPI interface connected to IC U8, U11, U12SPI interface (MISO, MOSI, MCLK) for temperature sensor U8, 3-axis accelerometer U11 and ADC/DAC U12
1temperature sensor IC, U8chip-select line for SPI interface
1accelerometer IC, U11chip-select line for SPI interface
1ADC/DAC IC , U12Synchronization line of ACD/DAC IC (active low control input)
1temperature sensor IC, U8interrupt line of critical temperature
1A81x14 pin headers J17 analog inputs or GPIO's, 1 pin analog reference voltage input
2pin headers J11 analog inputs or GPIO, 1 dedicated analog input
1B5pin header J44 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
88LEDs D2 ... D9Red user LEDs
6QSPI Flash memory, U56 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization
6FTDI FT2232H JTAG/UART adapter, U36 pins configurable as GPIO/UART or other serial interfaces
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
1User button S2user configurable
1Reset button S1 and pin J2-10low active reset line for FPGA reconfiguration

On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Subsections...

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

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Power-On Sequence

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Voltage Monitor Circuit

Power Rails

Bank Voltages

Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsReference Document










Recommended Operating Conditions

ParameterMinMaxUnitsReference Document










Physical Dimensions


Variants Currently In Production

Trenz shop TE0xxx overview page
English pageGerman page


Revision History

Hardware Revision History

DateRevisionNotePCNDocumentation Link
-01Prototypes--





Document Change History

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DateRevisionContributorDescription

  • initial release

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