Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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This TEC0330 reference design implements the SI5338 Configuration, DDR Configuration and PCIe Core Example Design.
Refer to http://trenz.org/tec0330-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Design supports following carriers:
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - AMD devices
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
See also: AMD Development Tools#XilinxSoftware-BasicUserGuides
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
Press 0 and enter to start "Module Selection Guide"
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
(Optional) BlockRam Firmware Update
Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into "<project folder>\firmware\microblaze_0\"
Copy "<project folder>\workspace\sdk\scu\Release\scu.elf" into "\firmware\microblaze_mcs_0\"
Regenerate Vivado Project or Update Bitfile only with "spi_bootloader.elf" and "scu_te0712.elf"
TE::hw_build_design -export_prebuilt TE::sw_run_vitis -all |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generate |
Type on Vivado TCL Console:
TE::pr_program_flash -swapp hello_tec0330 |
Not used on this Example.
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# # Default common settings that do not depend assembly variant # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
# # # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
#---------- #IIC to CPLD set_property PACKAGE_PIN W29 [get_ports SCF_0_cpld_25_scl] set_property PACKAGE_PIN W26 [get_ports SCF_0_cpld_19_oe] set_property PACKAGE_PIN V29 [get_ports SCF_0_cpld_24_sda] set_property IOSTANDARD LVCMOS18 [get_ports SCF_0_cpld_25_scl] set_property IOSTANDARD LVCMOS18 [get_ports SCF_0_cpld_19_oe] set_property IOSTANDARD LVCMOS18 [get_ports SCF_0_cpld_24_sda] #---------- #PCIe set_property PACKAGE_PIN E33 [get_ports FEX_4_N] set_property IOSTANDARD LVCMOS18 [get_ports FEX_4_N] set_property PACKAGE_PIN AD6 [get_ports {CLK_PCIe_100MHz_clk_p[0]}] #todo check auto placement: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets msys_i/axi_pcie3_0/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/CLK_TXOUTCLK] #---------- #Revision ID set_property PACKAGE_PIN AP27 [get_ports {REV_ID[0]}] set_property PACKAGE_PIN AN27 [get_ports {REV_ID[1]}] set_property PACKAGE_PIN AP26 [get_ports {REV_ID[2]}] set_property PACKAGE_PIN AP25 [get_ports {REV_ID[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {REV_ID[*]}] #---------- #QSPI set_property PACKAGE_PIN AL33 [get_ports {spi_rtl_ss_io[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {spi_rtl_ss_io[0]}] set_property PACKAGE_PIN AN33 [get_ports spi_rtl_io0_io] set_property PACKAGE_PIN AN34 [get_ports spi_rtl_io1_io] set_property PACKAGE_PIN AK34 [get_ports spi_rtl_io2_io] set_property PACKAGE_PIN AL34 [get_ports spi_rtl_io3_io] set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io0_io] set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io1_io] set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io2_io] set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io3_io] #---------- #CLKS ##SI5338_0_DDR3_CLK #diff 1.5V AG17/AH17 set_property PACKAGE_PIN AG17 [get_ports {SI5338_0_DDR3_CLK_clk_p}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {SI5338_0_DDR3_CLK_clk_p}] ##SI5338_1_MGTCLK_5338_C #diff MGT 1.8V AB6/AB5 set_property PACKAGE_PIN AB6 [get_ports {SI5338_1_MGTCLK_5338_C_clk_p[0]}] ###SI5338_3_LMK_CLK #diff MGT 1.8V to LMK CLKin1 ##SI5338_4_MGTCLK2_5338_C #diff MGT 1.8V H6/H5 set_property PACKAGE_PIN H6 [get_ports {SI5338_4_MGTCLK2_5338_C_clk_p[0]}] ##LMK_0_CLK_SYNTH_DCLKout0 #diff 1.8V AD29/AE29 set_property PACKAGE_PIN AD29 [get_ports {LMK_0_CLK_SYNTH_DCLKout0_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {LMK_0_CLK_SYNTH_DCLKout0_clk_p[0]}] set_property DIFF_TERM TRUE [get_ports {LMK_0_CLK_SYNTH_DCLKout0_clk_p[0]}] ##LMK_1_CLK_SYNTH_DCLKout1 #diff 1.8V AE31/AF31 set_property PACKAGE_PIN AE31 [get_ports {LMK_1_CLK_SYNTH_DCLKout1_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {LMK_1_CLK_SYNTH_DCLKout1_clk_p[0]}] set_property DIFF_TERM TRUE [get_ports {LMK_1_CLK_SYNTH_DCLKout1_clk_p[0]}] ###LMK_2_CLKIN_5338_P #diff 1.8Vto Si5338 IN1/IN2 ###LMK_3_CLK_SYNTH_SDCLKout3 #diff 1.8Vto N.C. ###LMK_4_CLK_SYNTH_SDCLKout4 #diff MGT 1.8V T6/T5 ###LMK_5_CLK_SYNTH_SDCLKout5 #diff 1.8Vto N.C. ###LMK_6_CLK_SYNTH_SDCLKout6 #diff 1.8Vto N.C. ###LMK_7_CLK_SYNTH_SDCLKout7 #diff MGT 1.8V F6/F5 ###LMK_8_CLK_SYNTH_SDCLKout8 #diff 1.8Vto N.C. ###LMK_9_CLK_SYNTH_SDCLKout9 #diff 1.8Vto N.C. ###LMK_10_CLK_SYNTH_SDCLKout10 #diff 1.8Vto N.C. ###LMK_11_CLK_SYNTH_SDCLKout11 #diff 1.8Vto N.C. ###LMK_12_CLK_SYNTH_SDCLKout12 #diff 1.8Vto N.C. ###LMK_13_CLK_SYNTH_SDCLKout13 #diff 1.8Vto N.C. #---------- |
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. spi_bootloaderTE modified SPI Bootloader from Henrik Brix Andersen. Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. eepromeeprom is a petalinux application that executes on startup. It reads the unique 48-bit MAC from the onboard eeprom and uses it to set the system MAC address. |
Template location: ./sw_lib/sw_apps/
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.
Descriptions:
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File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
To get content of older revision got to "Change History" of this page and select older document revision number.
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