Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
|
Important General Note:
|
Overview
Notes :
|
Zynq PS Design with Linux Example and Camera Demo.
Refer to http://trenz.org/te0726-info for the current online version of this manual and other available documentation.
Key Features
Notes :
|
|
Revision History
Notes :
|
|
Release Notes and Know Issues
Notes :
|
|
Requirements
Software
Notes :
|
|
Hardware
Notes :
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
*used as reference |
Design supports following carriers:
|
Additional HW Requirements:
|
Content
Notes :
|
For general structure and of the reference design, see Project Delivery - AMD devices
Design Sources
|
Additional Sources
|
Prebuilt
Notes :
|
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
|
Reference Design is available on:
Design Flow
Notes :
|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
(optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt
Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
- use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
- The build images are located in the "<plnx-proj-root>/images/linux" directory
- For 128MB and 64MB only:Netboot Offset must be reduced manually, see Config
- Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
Copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<DDR size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for Microblaze
- ...
Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
Note:
|
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select Create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
- Connect JTAG and power on the board
- Set the dip switch S1 to ON state. (JTAG only mode)
Note: Dip switch S1 exists only for boards with PCB REV04 or later.
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0726 (optional)
- After programming the QSPI set the dip switch S1 to OFF again. (QSPI boot mode)
- Copy image.ub and boot.scr on SD or USB
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Important: Do not copy Boot.bin on SD(is not used see SD note), only other files.
- Copy init.sh on SD-Card
- location: <design_name>/misc/sd/
- Insert SD-Card
SD
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (u-boot)
JTAG
Not used on this Example.
Usage
- Prepare HW like described in section Programming
- Connect UART USB (most cases same as JTAG)
Insert SD Card with image.ub
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrPower On PCB
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
Select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Auto login is activated. Therefore it is not necessary to give username and password.
Note: Wait until Linux boot finished
You can use a Linux shell now.
i2cdetect -y -r 5 (check I2C 1 Bus, Bus 0...5 possible) udhcpc (ETH0 check) lsusb (USB check)
- Camera stream will be enabled via init.sh script on SD
- Take image from camera (must be enabled with init.sh scripts):
- write image to webserver: fbgrab -d /dev/fb0 /srv/www/camera.png
- Display image on host PC: http://<ZynqBerry IP>/camera.png
System Design - Vivado
Note:
|
Block Design
|
PS Interfaces
Note:
|
Activated interfaces:
|
Constraints
Basic module constraints
# # Common BITGEN related settings for TE0726 # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] |
Design specific constraint
# # # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design |
#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o]
#set_property PACKAGE_PIN K15 [get_ports spdif_tx_o]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_1_tri_io[*]}]
# GPIO Pins
# GPIO2
set_property PACKAGE_PIN K15 [get_ports {GPIO_1_tri_io[0]}]
# GPIO3
set_property PACKAGE_PIN J14 [get_ports {GPIO_1_tri_io[1]}]
# GPIO4
set_property PACKAGE_PIN H12 [get_ports {GPIO_1_tri_io[2]}]
# GPIO5
set_property PACKAGE_PIN N14 [get_ports {GPIO_1_tri_io[3]}]
# GPIO6
set_property PACKAGE_PIN R15 [get_ports {GPIO_1_tri_io[4]}]
# GPIO7
set_property PACKAGE_PIN L14 [get_ports {GPIO_1_tri_io[5]}]
# GPIO8
set_property PACKAGE_PIN L15 [get_ports {GPIO_1_tri_io[6]}]
# GPIO9
set_property PACKAGE_PIN J13 [get_ports {GPIO_1_tri_io[7]}]
# GPIO10
set_property PACKAGE_PIN H14 [get_ports {GPIO_1_tri_io[8]}]
# GPIO11
set_property PACKAGE_PIN J15 [get_ports {GPIO_1_tri_io[9]}]
# GPIO12
set_property PACKAGE_PIN M15 [get_ports {GPIO_1_tri_io[10]}]
# GPIO13
set_property PACKAGE_PIN R13 [get_ports {GPIO_1_tri_io[11]}]
# GPIO16
set_property PACKAGE_PIN L13 [get_ports {GPIO_1_tri_io[12]}]
# GPIO17
set_property PACKAGE_PIN G11 [get_ports {GPIO_1_tri_io[13]}]
# GPIO18
set_property PACKAGE_PIN H11 [get_ports {GPIO_1_tri_io[14]}]
# GPIO19
set_property PACKAGE_PIN R12 [get_ports {GPIO_1_tri_io[15]}]
# GPIO20
set_property PACKAGE_PIN M14 [get_ports {GPIO_1_tri_io[16]}]
# GPIO21
set_property PACKAGE_PIN P15 [get_ports {GPIO_1_tri_io[17]}]
# GPIO22
set_property PACKAGE_PIN H13 [get_ports {GPIO_1_tri_io[18]}]
# GPIO23
set_property PACKAGE_PIN J11 [get_ports {GPIO_1_tri_io[19]}]
# GPIO24
set_property PACKAGE_PIN K11 [get_ports {GPIO_1_tri_io[20]}]
# GPIO25
set_property PACKAGE_PIN K13 [get_ports {GPIO_1_tri_io[21]}]
# GPIO26
set_property PACKAGE_PIN L12 [get_ports {GPIO_1_tri_io[22]}]
# GPIO27
set_property PACKAGE_PIN G12 [get_ports {GPIO_1_tri_io[23]}]
## DSI_D0_N
#set_property PACKAGE_PIN F13 [get_ports {GPIO_1_tri_io[24]}]
## DSI_D0_P
#set_property PACKAGE_PIN F14 [get_ports {GPIO_1_tri_io[25]}]
## DSI_D1_N
#set_property PACKAGE_PIN F12 [get_ports {GPIO_1_tri_io[26]}]
## DSI_D1_P
#set_property PACKAGE_PIN E13 [get_ports {GPIO_1_tri_io[27]}]
## DSI_C_N
#set_property PACKAGE_PIN E11 [get_ports {GPIO_1_tri_io[28]}]
## DSI_C_P
#set_property PACKAGE_PIN E12 [get_ports {GPIO_1_tri_io[29]}]
## CSI_D0_N
#set_property PACKAGE_PIN M11 [get_ports {GPIO_1_tri_io[30]}]
## CSI_D0_P
#set_property PACKAGE_PIN M10 [get_ports {GPIO_1_tri_io[31]}]
## CSI_D1_N
#set_property PACKAGE_PIN P14 [get_ports {GPIO_1_tri_io[32]}]
## CSI_D2_P
#set_property PACKAGE_PIN P13 [get_ports {GPIO_1_tri_io[33]}]
## CSI_C_N
#set_property PACKAGE_PIN N12 [get_ports {GPIO_1_tri_io[34]}]
## CSI_C_P
#set_property PACKAGE_PIN N11 [get_ports {GPIO_1_tri_io[35]}]
## PWM_R
##set_property PACKAGE_PIN N8 [get_ports {GPIO_1_tri_io[36]}]
## PWM_L
##set_property PACKAGE_PIN N7 [get_ports {GPIO_1_tri_io[37]}]
# PWM_R
set_property PACKAGE_PIN N8 [get_ports PWM_R]
# PWM_L
set_property PACKAGE_PIN N7 [get_ports PWM_L]
set_property IOSTANDARD LVCMOS33 [get_ports PWM_*]
|
set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p]
set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}]
set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}]
set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}]
set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}]
|
set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p]
set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}]
set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}]
set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}]
set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}]
set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}]
# RPI Camera 1
create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p]
# RPI Camera 2.1
#create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p]
|
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}]
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_3]
set_false_path -from [get_clocks clk_fpga_3] -to [get_clocks clk_fpga_0]
set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D]
set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D]
set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]
set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]
|
Software Design - Vitis
Note:
|
For SDK project creation, follow instructions from:
Application
---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2023.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 2023.2 FSBL General:
Module Specific:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2023.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
SDK Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2022.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- enable VTC and VDMA cores for camera access
hello_te0726
Hello TE0726 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
Note:
|
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
For 512MB variant:
- No change
For 64MB variant only:
- CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x2000000
For 128MB variant only:
- CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x4000000
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
Device Tree
/include/ "system-conf.dtsi"
/ {
};
/ {
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
hdmi_fb_reserved_region@1FC00000 {
//compatible = "removed-dma-pool";
compatible = "shared-dma-pool";
no-map;
// 512M (M modules)
reg = <0x1FC00000 0x400000>;
// 128M (R modules)
//reg = <0x7C00000 0x400000>;
};
// Second framebuffer for direct data streaming from camera to monitor is not needed.
//camera_fb_reserved_region@1FC00000 {
// //compatible = "removed-dma-pool";
// compatible = "shared-dma-pool";
// no-map;
// // 512M (M modules)
// reg = <0x1FC00000 0x400000>;
// // 128M (R modules)
// //reg = <0x7800000 0x400000>;
//};
};
hdmi_fb: framebuffer@1FC00000 { // HDMI out
compatible = "simple-framebuffer";
// 512M (M modules)
reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p
// 128M (R modules)
//reg = <0x7C00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
status = "okay";
};
//camera_fb: framebuffer@0x1FC00000 { // CAMERA in
// compatible = "simple-framebuffer";
// // 512M (M modules)
// reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p
// // 128M (R modules)
// //reg = <0x7800000 (1280 * 720 * 4)>; // 720p
// width = <1280>; // 720p
// height = <720>; // 720p
// stride = <(1280 * 4)>; // 720p
// format = "a8b8g8r8";
//};
vcc_3V3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vccaux-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <50000000>;
partition@0x00000000 {
label = "boot";
reg = <0x00000000 0x00500000>;
};
partition@0x00500000 {
label = "bootenv";
reg = <0x00500000 0x00020000>;
};
partition@0x00520000 {
label = "kernel";
reg = <0x00520000 0x00a80000>;
};
partition@0x00fa0000 {
label = "spare";
reg = <0x00fa0000 0x00000000>;
};
};
};
/*
* We need to disable Linux VDMA driver as VDMA
* already configured in FSBL
*/
&video_in_axi_vdma_0 {
status = "disabled";
};
&video_out_axi_vdma_0 {
status = "disabled";
};
&video_out_v_tc_0 {
//xilinx-vtc: probe of 43c20000.v_tc failed with error -2
status = "disabled";
};
&gpio0 {
interrupt-controller;
#interrupt-cells = <2>;
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
i2cmux0: i2cmux@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c1@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
id_eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
};
i2c1@1 { // Display Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c1@2 { // HDMI Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c1@3 { // Camera Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
usb-phy = <&usb_phy0>;
} ;
/*
* Sound configuration
*/
/{
/* Use S/PDIF transmitter as codec required by simple-audio-card */
playback_codec: playback-codec {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
/* Use S/PDIF receiver as codec required by simple-audio-card */
record_codec: record-codec {
compatible = "linux,spdif-dir";
#sound-dai-cells = <0>;
};
sound {
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,widgets =
"Microphone", "In Jack",
"Line", "Line In Jack",
"Line", "Line Out Jack",
"Headphone", "Out Jack";
simple-audio-card,routing =
"Out Jack", "te-out",
"te-in", "In Jack";
i2s_receiver_0:i2s_receiver@43C10000 {
compatible = "xlnx,i2s-receiver-1.0";
clock-names = "s_axi_ctrl_aclk", "aud_mclk", "m_axis_aud_aclk";
aud_mclk = <4081632>;
reg = <0x0 0x43C10000 0x0 0x10000>;
//xlnx,dwidth = <0x18>; //I2S Data Width 24 bit
xlnx,dwidth = <0x10>; //I2S Data Width 16 bit
xlnx,num-channels = <2>;
xlnx,snd-pcm = <&audio_formatter_0>;
};
i2s_transmitter_0:i2s_transmitter@43C20000 {
compatible = "xlnx,i2s-transmitter-1.0";
clock-names = "s_axi_ctrl_aclk", "aud_mclk", "s_axis_aud_aclk";
aud_mclk = <4081632>;
reg = <0x0 0x43C20000 0x0 0x10000>;
//xlnx,dwidth = <0x18>; //I2S Data Width 24 bit
xlnx,dwidth = <0x10>; //I2S Data Width 16 bit
xlnx,num-channels = <2>;
xlnx,snd-pcm = <&audio_formatter_0>;
};
audio_formatter_0:audio_formatter@43C00000 {
compatible = "xlnx,audio-formatter-1.0";
interrupt-names = "irq_mm2s", "irq_s2mm";
reg = <0x0 0x43C00000 0x0 0x1000>;
xlnx,tx = <&i2s_transmitter_0>;
xlnx,rx = <&i2s_receiver_0>;
clock-names = "s_axi_lite_aclk", "m_axis_mm2s_aclk", "aud_mclk", "s_axis_s2mm_aclk";
aud_mclk = <12307691>;
};
playback_link: simple-audio-card,dai-link@0 {
reg = <0>;
format = "i2s";
bitclock-master = <&p_codec_dai>;
frame-master = <&p_codec_dai>;
p_cpu_dai: cpu {
sound-dai = <&i2s_transmitter_0>;
};
p_platform_dai: plat {
sound-dai = <&audio_formatter_0>;
};
p_codec_dai: codec {
sound-dai = <&playback_codec>;
};
};
record_link: simple-audio-card,dai-link@1 {
reg = <1>;
format = "i2s";
bitclock-master = <&r_codec_dai>;
frame-master = <&r_codec_dai>;
r_cpu_dai: cpu {
sound-dai = <&i2s_receiver_0>;
};
r_platform_dai: plat {
sound-dai = <&audio_formatter_0>;
};
r_codec_dai: codec {
sound-dai = <&record_codec>;
};
};
};
};
/*
* We need to disable Linux XADC driver to use XADC for audio recording
*/
&adc {
status = "disabled";
};
|
Kernel
Start with petalinux-config -c kernel
Changes:
CONFIG_MII=y
CONFIG_XILINX_GMII2RGMII=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_AX8817X=y
CONFIG_USB_NET_AX88179_178A=y
CONFIG_USB_NET_CDCETHER=y
# CONFIG_USB_NET_CDC_EEM is not set
CONFIG_USB_NET_CDC_NCM=y
# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
# CONFIG_USB_NET_CDC_MBIM is not set
# CONFIG_USB_NET_DM9601 is not set
# CONFIG_USB_NET_SR9700 is not set
# CONFIG_USB_NET_SR9800 is not set
# CONFIG_USB_NET_SMSC75XX is not set
CONFIG_USB_NET_SMSC95XX=y
# CONFIG_USB_NET_GL620A is not set
CONFIG_USB_NET_NET1080=y
# CONFIG_USB_NET_PLUSB is not set
# CONFIG_USB_NET_MCS7830 is not set
# CONFIG_USB_NET_RNDIS_HOST is not set
CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
CONFIG_USB_NET_CDC_SUBSET=y
# CONFIG_USB_ALI_M5632 is not set
# CONFIG_USB_AN2720 is not set
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
# CONFIG_USB_EPSON2888 is not set
# CONFIG_USB_KC2190 is not set
CONFIG_USB_NET_ZAURUS=y
# CONFIG_USB_NET_CX82310_ETH is not set
# CONFIG_USB_NET_KALMIA is not set
# CONFIG_USB_NET_QMI_WWAN is not set
# CONFIG_USB_NET_INT51X1 is not set
# CONFIG_USB_SIERRA_NET is not set
# CONFIG_USB_VL600 is not set
# CONFIG_USB_NET_CH9200 is not set
# CONFIG_USB_NET_AQC111 is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FRAMEBUFFER_CONSOLE is not set
CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_USBIP_CORE=y
# CONFIG_USBIP_VHCI_HCD is not set
# CONFIG_USBIP_HOST is not set
# CONFIG_USBIP_VUDC is not set
# CONFIG_USBIP_DEBUG is not set
CONFIG_SND_SOC_XILINX_I2S=y
CONFIG_SND_SOC_XILINX_PL_SND_CARD=y
CONFIG_SND_SOC_HDMI_CODEC=n
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=n
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y
CONFIG_SND_SOC_XILINX_SPDIF=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_packagegroup-petalinux-utils = y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- CONFIG_alsa-plugins = y
- CONFIG_alsa-lib-dev = y
- CONFIG_libasound = y
- CONFIG_alsa-conf-base = y
- CONFIG_alsa-conf = y
- CONFIG_alsa-utils = y
- CONFIG_alsa-utils-aplay = y
- CONFIG_busybox-httpd = y
- CONFIG_util-linux-mount = y
- CONFIG_util-linux-umount = y
- CONFIG_util-linux-mountpoint = y
- CONFIG_linux-blkid = y
CONFIG_auto-login=y
CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
rpicam
Application used to enable and configure Raspbery Pi camera module
See: \os\petalinux\project-spec\meta-user\recipes-apps\rpicam\files
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
See: \os\petalinux\project-spec\meta-user\recipes-apps\webfwu\files
Additional Software
| Note: |
No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|
|
Legal Notices
|
|