Template Revision 2.8 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"


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Important General Note:

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    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):


        Create DrawIO object here: Attention if you copy from other page, use


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Table of contents

Overview

Notes :

Zynq PS Design with Linux Example with video and audio configuration.

Refer to http://trenz.org/te0726-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • Add basic key futures, which can be tested with the design


  • Vitis/Vivado 2019.2
  • RPI Camera 1.3 or 2.1
  • VIDEO/AUDIO (plus video/audio player)
  • HDMI
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • Special FSBL for QSPI programming

Revision History

Notes :

  • add every update file on the download
  • add design changes on description


DateVivadoProject BuiltAuthorsDescription
2020-03-252019.2TE0726-zynqberrydemo3_noprebuilt-vivado_2019.2-build_8_20200325082001.zip
TE0726-zynqberrydemo3-vivado_2019.2-build_8_20200325081946.zip
Mohsen Chamanbaz/John Hartfiel
  • script update
2020-02-202019.2TE0726-zynqberrydemo3_noprebuilt-vivado_2019.2-build_5_20200214101637.zip
TE0726-zynqberrydemo3-vivado_2019.2-build_5_20200214101624.zip
Mohsen Chamanbaz
  • update with Vivado 2019.2
2019-12-192018.3te0726-zynqberrydemo3-vivado_2018.3-build_10_20200114090815.zip
te0726-zynqberrydemo3_noprebuilt-vivado_2018.3-build_10_20200114090645.zip
Mohsen Chamanbaz
  • update with Vivado 2018.3
2019-02-122018.2te0726-zynqberrydemo3-vivado_2018.2-build_04_20190212141216.zip
te0726-zynqberrydemo3_noprebuilt-vivado_2018.2-build_04_20190212141236.zip
Oleksandr Kiyenko
  • add missing fgrab in petalinux template
2018-12-05

2018.2

te0726-zynqberrydemo3-vivado_2018.2-build_03_20181128113130.zip
te0726-zynqberrydemo3_noprebuilt-vivado_2018.2-build_03_20181128113146.zip
Oleksandr Kiyenko
  • initial release


Release Notes and Know Issues

Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


IssuesDescriptionWorkaroundTo be fixed version
Flash Programming failed with 19.2Depending on Flash content Flash programming failed with provided fsbl_flash (Xilinx AR# 70548 )2019.2 version
  • Option1:
    • In case Flash is empty, use fsbl_flash on programming GUI 
    • In case Flash is programmed use normal fsbl on programming GUI
  • Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
---


Requirements

Software

Notes :

  • list of software which was used to generate the design


SoftwareVersionNote
Vitis2019.2needed, Vivado ist included into Vitis installlation
PetaLinux2019.2needed


Hardware

Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
te0726-01 01 REV0164MB LPDDR216MB
not included, user modifications are needed
te0726-03r r REV02, REV03128MB DDR3L16MB
not included, user modifications are needed
te0726-03m m REV02, REV03512MB DDR3L16MB

te0726-03-07s-1c7sREV03512MB DDR3L16MB


Design supports following carriers:

Carrier ModelNotes
---




Additional HW Requirements:

Additional HardwareNotes
USB PowerUse USB2.0 or higher for power supply via USB
USB CableConnect to USB2 or better USB3 Hub for proper power supply over USB
Headphones
--
Raspberry Pi Camera Rev 1.3 or Camera Rev 2.1Betaimplemenetation of REV2.1(not complette stable)
MonitorDELL Model Number: U2412Mc
HDMI Cable--


Content

Notes :

  • the content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

TypeLocationNotes
init.sh<design name>/misc/init_scriptAdditional Initialization Script for Linux


Prebuilt

Notes :

  • prebuilt files
  • Template Table:

    • File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported XSA
    1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
      2. For 128MB and 64MB only:Netboot Offset must be reduced manually, see TE0726 Zynqberry Demo3#Config
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\<DDR size>" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\\<DDR size>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Note:

  • Programming and Startup procedure

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

  1. Connect JTAG and power module (TE0726 can be powered via JTAG USB or external)
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash -swapp hello_te0726" possible
  4. Build Image.ub in Petalinux 
  5. Copy the Petalinux image.ub on SD-Card
  6. Copy init.sh on SD-Card
  7. Insert SD-Card

SD

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (u-boot)

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described in section TE0726 Zynqberry Demo3#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Insert SD Card with image.ub
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads U-boot from QSPI into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
      Note: Wait until Linux boot finished For Linux Login use:
      1. User Name: root
      2. Password: root
  3. You can use a Linux shell now.
    1. I2C 1 Bus type: i2cdetect -y -r 5
      Bus 0...5 possible
    2. ETH0 works with udhcpc
    3. USB: insert USB device
  4. Start Video with "play <video file>"
    1. "play" is alias to ffmpeg with some parameters for video and audio, type "alias" to see configuration
    2. for videos with higher resolution, disable audio on ffmpeg configuration
  5. Start Audio with "aplay <audio files>"
  6. Take image from camera (must be enabled with init.sh scripts):
    1. write image to webserver: fbgrab -d /dev/fb1 /srv/www/camera.png
    2. Display image on host PC: http://<ZynqBerry IP>/camera.png

System Design - Vivado

Note:

  • Description of Block Design, Constraints... BD Pictures from Export...

Block Design

PS Interfaces

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

TypeNote
DDR---
QSPIMIO
USB0MIO, ETH over USB
SD1MIO
UART1MIO
I2C0EMIO
I2C1MIO
GPIOMIO / EMIO
USB RSTMIO
TTC0..1MIO
WDTMIO
AXI HP0..1
DMA0..1


Constraints

Basic module constraints

#
# Common BITGEN related settings for TE0726
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constraint

#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]


#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o]
#set_property PACKAGE_PIN K15 [get_ports spdif_tx_o]

set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_1_tri_io[*]}]
# GPIO Pins
# GPIO2
set_property PACKAGE_PIN K15 [get_ports {GPIO_1_tri_io[0]}]
# GPIO3
set_property PACKAGE_PIN J14 [get_ports {GPIO_1_tri_io[1]}]
# GPIO4
set_property PACKAGE_PIN H12 [get_ports {GPIO_1_tri_io[2]}]
# GPIO5
set_property PACKAGE_PIN N14 [get_ports {GPIO_1_tri_io[3]}]
# GPIO6
set_property PACKAGE_PIN R15 [get_ports {GPIO_1_tri_io[4]}]
# GPIO7
set_property PACKAGE_PIN L14 [get_ports {GPIO_1_tri_io[5]}]
# GPIO8
set_property PACKAGE_PIN L15 [get_ports {GPIO_1_tri_io[6]}]
# GPIO9
set_property PACKAGE_PIN J13 [get_ports {GPIO_1_tri_io[7]}]
# GPIO10
set_property PACKAGE_PIN H14 [get_ports {GPIO_1_tri_io[8]}]
# GPIO11
set_property PACKAGE_PIN J15 [get_ports {GPIO_1_tri_io[9]}]
# GPIO12
set_property PACKAGE_PIN M15 [get_ports {GPIO_1_tri_io[10]}]
# GPIO13
set_property PACKAGE_PIN R13 [get_ports {GPIO_1_tri_io[11]}]
# GPIO16
set_property PACKAGE_PIN L13 [get_ports {GPIO_1_tri_io[12]}]
# GPIO17
set_property PACKAGE_PIN G11 [get_ports {GPIO_1_tri_io[13]}]
# GPIO18
set_property PACKAGE_PIN H11 [get_ports {GPIO_1_tri_io[14]}]
# GPIO19
set_property PACKAGE_PIN R12 [get_ports {GPIO_1_tri_io[15]}]
# GPIO20
set_property PACKAGE_PIN M14 [get_ports {GPIO_1_tri_io[16]}]
# GPIO21
set_property PACKAGE_PIN P15 [get_ports {GPIO_1_tri_io[17]}]
# GPIO22
set_property PACKAGE_PIN H13 [get_ports {GPIO_1_tri_io[18]}]
# GPIO23
set_property PACKAGE_PIN J11 [get_ports {GPIO_1_tri_io[19]}]
# GPIO24
set_property PACKAGE_PIN K11 [get_ports {GPIO_1_tri_io[20]}]
# GPIO25
set_property PACKAGE_PIN K13 [get_ports {GPIO_1_tri_io[21]}]
# GPIO26
set_property PACKAGE_PIN L12 [get_ports {GPIO_1_tri_io[22]}]
# GPIO27
set_property PACKAGE_PIN G12 [get_ports {GPIO_1_tri_io[23]}]

## DSI_D0_N
#set_property PACKAGE_PIN F13 [get_ports {GPIO_1_tri_io[24]}]
## DSI_D0_P
#set_property PACKAGE_PIN F14 [get_ports {GPIO_1_tri_io[25]}]
## DSI_D1_N
#set_property PACKAGE_PIN F12 [get_ports {GPIO_1_tri_io[26]}]
## DSI_D1_P
#set_property PACKAGE_PIN E13 [get_ports {GPIO_1_tri_io[27]}]
## DSI_C_N
#set_property PACKAGE_PIN E11 [get_ports {GPIO_1_tri_io[28]}]
## DSI_C_P
#set_property PACKAGE_PIN E12 [get_ports {GPIO_1_tri_io[29]}]

## CSI_D0_N
#set_property PACKAGE_PIN M11 [get_ports {GPIO_1_tri_io[30]}]
## CSI_D0_P
#set_property PACKAGE_PIN M10 [get_ports {GPIO_1_tri_io[31]}]
## CSI_D1_N
#set_property PACKAGE_PIN P14 [get_ports {GPIO_1_tri_io[32]}]
## CSI_D2_P
#set_property PACKAGE_PIN P13 [get_ports {GPIO_1_tri_io[33]}]
## CSI_C_N
#set_property PACKAGE_PIN N12 [get_ports {GPIO_1_tri_io[34]}]
## CSI_C_P
#set_property PACKAGE_PIN N11 [get_ports {GPIO_1_tri_io[35]}]
## PWM_R
##set_property PACKAGE_PIN N8 [get_ports {GPIO_1_tri_io[36]}]
## PWM_L
##set_property PACKAGE_PIN N7 [get_ports {GPIO_1_tri_io[37]}]

# PWM_R
set_property PACKAGE_PIN N8 [get_ports PWM_R]
# PWM_L
set_property PACKAGE_PIN N7 [get_ports PWM_L]
set_property IOSTANDARD LVCMOS33 [get_ports PWM_*]




set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p]
set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}]
set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}]
set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}]
set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}]




set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p]
set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}]
set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}]
set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}]
set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}]
set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}]
# RPI Camera 1
create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p]
# RPI Camera 2.1
#create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p]




set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}]
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_3]
set_false_path -from [get_clocks clk_fpga_3] -to [get_clocks clk_fpga_0]

set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D]
set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D]

set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]
set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]




Software Design - Vitis

<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

Vitis

Application

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2018.3 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2018.3 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

SDK template in ./sw_lib/sw_apps/ available.

zynq_fsbl

TE modified 2019.2 FSBL

General:

Module Specific:

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

hello_te0726

Hello TE0726 is a Xilinx Hello World example as an endless loop instead of one console output and TE FSBL screen on HDMI Monitor.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

For 64MB variant only:

For 128MB variant only:

U-Boot

Start with petalinux-config -c u-boot
Changes:

Device Tree

/include/ "system-conf.dtsi"
/ {
};


/ {
    #address-cells = <1>;
    #size-cells = <1>;

    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        hdmi_fb_reserved_region@1FC00000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1FC00000 0x400000>;
            // 128M (R modules)
            //reg = <0x7C00000 0x400000>;
        };
        camera_fb_reserved_region@1F800000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1F800000 0x400000>;
            // 128M (R modules)
            //reg = <0x7800000 0x400000>;
        };

    };

    hdmi_fb: framebuffer@0x1FC00000 {           // HDMI out 
        compatible = "simple-framebuffer";
        // 512M (M modules)
        reg = <0x1FC00000 (1280 * 720 * 4)>;    // 720p
        // 128M (R modules)
        //reg = <0x7C00000 (1280 * 720 * 4)>;   // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
        status = "okay";
    };

    camera_fb: framebuffer@0x1F800000 {         // CAMERA in
        compatible = "simple-framebuffer";
        // 512M (M modules)
        reg = <0x1F800000 (1280 * 720 * 4)>;    // 720p
        // 128M (R modules)
        //reg = <0x7800000 (1280 * 720 * 4)>;   // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
    };

    vcc_3V3: fixedregulator@0 {
        compatible = "regulator-fixed";
        regulator-name = "vccaux-supply";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        regulator-always-on;
    };
};

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <50000000>;
        partition@0x00000000 {
            label = "boot";
            reg = <0x00000000 0x00500000>;
        };
        partition@0x00500000 {
            label = "bootenv";
            reg = <0x00500000 0x00020000>;
        };
        partition@0x00520000 {
            label = "kernel";
            reg = <0x00520000 0x00a80000>;
        };
        partition@0x00fa0000 {
            label = "spare";
            reg = <0x00fa0000 0x00000000>;
        };
    };
};

/*
* We need to disable Linux VDMA driver as VDMA
* already configured in FSBL
*/
&video_in_axi_vdma_0 {
   status = "disabled";
};

&video_out_axi_vdma_0 {
   status = "disabled";
};

&video_out_v_tc_0 {
    //xilinx-vtc: probe of 43c20000.v_tc failed with error -2
    status = "disabled";
};

&gpio0 {
    interrupt-controller;
    #interrupt-cells = <2>;
};

&i2c1 {
    #address-cells = <1>;
    #size-cells = <0>;

    i2cmux0: i2cmux@70  {
        compatible = "nxp,pca9544";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x70>;


        i2c1@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;

            id_eeprom@50 {
                compatible = "atmel,24c32";
                reg = <0x50>;
            };

        };
        i2c1@1 {    // Display Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c1@2 {    // HDMI Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c1@3 {    // Camera Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
    };

};

/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    usb-phy = <&usb_phy0>;
} ;

/*
* Sound configuration
*/

/{
    // Custom driver based on spdif-transmitter
    te_audio: dummy_codec_te {
        compatible = "te,te-audio";
        #sound-dai-cells = <0>;
    };

    // Simple Audio Card from AXI_I2S and custom XADC audio input and
    // PWM audio output cores
    sound {
        compatible = "simple-audio-card";
        simple-audio-card,name = "TE0726-PWM-Audio";
        simple-audio-card,format = "i2s";
        simple-audio-card,widgets =
            "Microphone", "In Jack",
            "Line", "Line In Jack",
            "Line", "Line Out Jack",
            "Headphone", "Out Jack";

        simple-audio-card,routing =
            "Out Jack", "te-out",
            "te-in", "In Jack";

        simple-audio-card,cpu {
            sound-dai = <&audio_axi_i2s_adi_0>;
        };
        simple-audio-card,codec {
            sound-dai = <&te_audio>;
        };
    };
};

&audio_axi_i2s_adi_0 {
    compatible = "adi,axi-i2s-1.00.a";
    reg = <0x43c00000 0x1000>;
    clocks = <&clkc 15>, <&clkc 18>; // FCLK_CLK0, FCLK_CLK3
    clock-names = "axi", "ref";
    dmas = <&dmac_s 0 &dmac_s 1>;
    dma-names = "tx", "rx";
    #sound-dai-cells = <0>;
};

/*
* We need to disable Linux XADC driver to use XADC for audio recording
*/
&adc {
    status = "disabled";
};

Kernel

Start with petalinux-config -c kernel

Changes:

Rootfs

Start with petalinux-config -c rootfs

Avtivate:

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

rpicam

Application used to enable and configure Raspbery Pi camera module

See: \os\petalinux\project-spec\meta-user\recipes-apps\rpicam\files

fbgrab

Application used to take screenshot from camera

See: \os\petalinux\project-spec\meta-user\recipes-apps\fgrab

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

See: \os\petalinux\project-spec\meta-user\recipes-apps\webfwu\files

Kernel Modules

te-audio-codec

Simple module stab to use audio interface.

See: \os\petalinux\project-spec\meta-user\recipes-modules\te-audio-codec\files

Additional Software

Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateDocument Revision

Authors

Description

  • typo
  • Programming issue note
2020-03-25v.14John Hartfiel
  • script update
2020-02-20v.13Mohsen Chamanbaz
  • Vivado 2019.2 release
2020-01-14v.11Mohsen Chamanbaz
  • Vivado 2018.3 release
2019-02-12v.10John Hartfiel
  • design linux source update

2018-12-05

v.7John Hartfiel
  • Vivado 2018.2 release
--all

--


Legal Notices