Template Revision 2.1 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) --> <style> .wrapped{ width: 100% !important; max-width: 1200px !important; } </style> |
Important General Note:
|
Table of contents |
Notes :
|
Zynq PS Design with Linux Example.
Refer to http://trenz.org/te0726-info for the current online version of this manual and other available documentation.
Notes :
|
|
Notes :
|
|
Notes :
|
|
Notes :
|
|
Notes :
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
|
Design supports following carriers:
|
Additional HW Requirements:
|
Notes :
|
For general structure and of the reference design, see Project Delivery
|
|
Notes :
|
|
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
|
Reference Design is available on:
Notes :
|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note:
|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (u-boot)
Not used on this Example.
Note:
|
Activated interfaces:
|
# # Common BITGEN related settings for TE0726 # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
# # # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o] #set_property PACKAGE_PIN K15 [get_ports spdif_tx_o] set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_1_tri_io[*]}] # GPIO Pins # GPIO2 set_property PACKAGE_PIN K15 [get_ports {GPIO_1_tri_io[0]}] # GPIO3 set_property PACKAGE_PIN J14 [get_ports {GPIO_1_tri_io[1]}] # GPIO4 set_property PACKAGE_PIN H12 [get_ports {GPIO_1_tri_io[2]}] # GPIO5 set_property PACKAGE_PIN N14 [get_ports {GPIO_1_tri_io[3]}] # GPIO6 set_property PACKAGE_PIN R15 [get_ports {GPIO_1_tri_io[4]}] # GPIO7 set_property PACKAGE_PIN L14 [get_ports {GPIO_1_tri_io[5]}] # GPIO8 set_property PACKAGE_PIN L15 [get_ports {GPIO_1_tri_io[6]}] # GPIO9 set_property PACKAGE_PIN J13 [get_ports {GPIO_1_tri_io[7]}] # GPIO10 set_property PACKAGE_PIN H14 [get_ports {GPIO_1_tri_io[8]}] # GPIO11 set_property PACKAGE_PIN J15 [get_ports {GPIO_1_tri_io[9]}] # GPIO12 set_property PACKAGE_PIN M15 [get_ports {GPIO_1_tri_io[10]}] # GPIO13 set_property PACKAGE_PIN R13 [get_ports {GPIO_1_tri_io[11]}] # GPIO16 set_property PACKAGE_PIN L13 [get_ports {GPIO_1_tri_io[12]}] # GPIO17 set_property PACKAGE_PIN G11 [get_ports {GPIO_1_tri_io[13]}] # GPIO18 set_property PACKAGE_PIN H11 [get_ports {GPIO_1_tri_io[14]}] # GPIO19 set_property PACKAGE_PIN R12 [get_ports {GPIO_1_tri_io[15]}] # GPIO20 set_property PACKAGE_PIN M14 [get_ports {GPIO_1_tri_io[16]}] # GPIO21 set_property PACKAGE_PIN P15 [get_ports {GPIO_1_tri_io[17]}] # GPIO22 set_property PACKAGE_PIN H13 [get_ports {GPIO_1_tri_io[18]}] # GPIO23 set_property PACKAGE_PIN J11 [get_ports {GPIO_1_tri_io[19]}] # GPIO24 set_property PACKAGE_PIN K11 [get_ports {GPIO_1_tri_io[20]}] # GPIO25 set_property PACKAGE_PIN K13 [get_ports {GPIO_1_tri_io[21]}] # GPIO26 set_property PACKAGE_PIN L12 [get_ports {GPIO_1_tri_io[22]}] # GPIO27 set_property PACKAGE_PIN G12 [get_ports {GPIO_1_tri_io[23]}] ## DSI_D0_N #set_property PACKAGE_PIN F13 [get_ports {GPIO_1_tri_io[24]}] ## DSI_D0_P #set_property PACKAGE_PIN F14 [get_ports {GPIO_1_tri_io[25]}] ## DSI_D1_N #set_property PACKAGE_PIN F12 [get_ports {GPIO_1_tri_io[26]}] ## DSI_D1_P #set_property PACKAGE_PIN E13 [get_ports {GPIO_1_tri_io[27]}] ## DSI_C_N #set_property PACKAGE_PIN E11 [get_ports {GPIO_1_tri_io[28]}] ## DSI_C_P #set_property PACKAGE_PIN E12 [get_ports {GPIO_1_tri_io[29]}] ## CSI_D0_N #set_property PACKAGE_PIN M11 [get_ports {GPIO_1_tri_io[30]}] ## CSI_D0_P #set_property PACKAGE_PIN M10 [get_ports {GPIO_1_tri_io[31]}] ## CSI_D1_N #set_property PACKAGE_PIN P14 [get_ports {GPIO_1_tri_io[32]}] ## CSI_D2_P #set_property PACKAGE_PIN P13 [get_ports {GPIO_1_tri_io[33]}] ## CSI_C_N #set_property PACKAGE_PIN N12 [get_ports {GPIO_1_tri_io[34]}] ## CSI_C_P #set_property PACKAGE_PIN N11 [get_ports {GPIO_1_tri_io[35]}] ## PWM_R ##set_property PACKAGE_PIN N8 [get_ports {GPIO_1_tri_io[36]}] ## PWM_L ##set_property PACKAGE_PIN N7 [get_ports {GPIO_1_tri_io[37]}] # PWM_R set_property PACKAGE_PIN N8 [get_ports PWM_R] # PWM_L set_property PACKAGE_PIN N7 [get_ports PWM_L] set_property IOSTANDARD LVCMOS33 [get_ports PWM_*] |
set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}] set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}] |
set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] set_property INTERNAL_VREF 0.6 [get_iobanks 34] set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] # RPI Camera 1 create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p] # RPI Camera 2.1 #create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p] |
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}] set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}] set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_3] set_false_path -from [get_clocks clk_fpga_3] -to [get_clocks clk_fpga_0] set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D] set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D] set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D] set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D] |
<!-- optional chapter separate sections for different apps --> |
For SDK project creation, follow instructions from:
SDK template in ./sw_lib/sw_apps/ available.
TE modified 2018.2 FSBL
TE modified 2018.2 FSBL
Changes:
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Hello TE0726 is a Xilinx Hello World example as an endless loop instead of one console output and TE FSBL screen on HDMI Monitor.
Note:
|
For PetaLinux installation and project creation, follow instructions from:
For 64MB variant only:
For 128MB variant only:
No changes.
/include/ "system-conf.dtsi" / { }; / { #address-cells = <1>; #size-cells = <1>; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; hdmi_fb_reserved_region@1FC00000 { compatible = "removed-dma-pool"; no-map; // 512M (M modules) reg = <0x1FC00000 0x400000>; // 128M (R modules) //reg = <0x7C00000 0x400000>; }; camera_fb_reserved_region@1F800000 { compatible = "removed-dma-pool"; no-map; // 512M (M modules) reg = <0x1F800000 0x400000>; // 128M (R modules) //reg = <0x7800000 0x400000>; }; }; hdmi_fb: framebuffer@0x1FC00000 { // HDMI out compatible = "simple-framebuffer"; // 512M (M modules) reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p // 128M (R modules) //reg = <0x7C00000 (1280 * 720 * 4)>; // 720p width = <1280>; // 720p height = <720>; // 720p stride = <(1280 * 4)>; // 720p format = "a8b8g8r8"; status = "okay"; }; camera_fb: framebuffer@0x1F800000 { // CAMERA in compatible = "simple-framebuffer"; // 512M (M modules) reg = <0x1F800000 (1280 * 720 * 4)>; // 720p // 128M (R modules) //reg = <0x7800000 (1280 * 720 * 4)>; // 720p width = <1280>; // 720p height = <720>; // 720p stride = <(1280 * 4)>; // 720p format = "a8b8g8r8"; }; vcc_3V3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vccaux-supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; partition@0x00000000 { label = "boot"; reg = <0x00000000 0x00500000>; }; partition@0x00500000 { label = "bootenv"; reg = <0x00500000 0x00020000>; }; partition@0x00520000 { label = "kernel"; reg = <0x00520000 0x00a80000>; }; partition@0x00fa0000 { label = "spare"; reg = <0x00fa0000 0x00000000>; }; }; }; /* * We need to disable Linux VDMA driver as VDMA * already configured in FSBL */ &video_in_axi_vdma_0 { status = "disabled"; }; &video_out_axi_vdma_0 { status = "disabled"; }; &video_out_v_tc_0 { //xilinx-vtc: probe of 43c20000.v_tc failed with error -2 status = "disabled"; }; &gpio0 { interrupt-controller; #interrupt-cells = <2>; }; &i2c1 { #address-cells = <1>; #size-cells = <0>; i2cmux0: i2cmux@70 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c1@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; id_eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c1@1 { // Display Interface Connector #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c1@2 { // HDMI Interface Connector #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c1@3 { // Camera Interface Connector #address-cells = <1>; #size-cells = <0>; reg = <3>; }; }; }; /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { usb-phy = <&usb_phy0>; } ; /* * Sound configuration */ /{ // Custom driver based on spdif-transmitter te_audio: dummy_codec_te { compatible = "te,te-audio"; #sound-dai-cells = <0>; }; // Simple Audio Card from AXI_I2S and custom XADC audio input and // PWM audio output cores sound { compatible = "simple-audio-card"; simple-audio-card,name = "TE0726-PWM-Audio"; simple-audio-card,format = "i2s"; simple-audio-card,widgets = "Microphone", "In Jack", "Line", "Line In Jack", "Line", "Line Out Jack", "Headphone", "Out Jack"; simple-audio-card,routing = "Out Jack", "te-out", "te-in", "In Jack"; simple-audio-card,cpu { sound-dai = <&audio_axi_i2s_adi_0>; }; simple-audio-card,codec { sound-dai = <&te_audio>; }; }; }; &audio_axi_i2s_adi_0 { compatible = "adi,axi-i2s-1.00.a"; reg = <0x43c00000 0x1000>; clocks = <&clkc 15>, <&clkc 18>; // FCLK_CLK0, FCLK_CLK3 clock-names = "axi", "ref"; dmas = <&dmac_s 0 &dmac_s 1>; dma-names = "tx", "rx"; #sound-dai-cells = <0>; }; /* * We need to disable Linux XADC driver to use XADC for audio recording */ &adc { status = "disabled"; }; |
Activate:
Deactivate:
Activate:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Add on new project:
Application used to enable and configure Raspbery Pi camera module
See: \os\petalinux\project-spec\meta-user\recipes-apps\rpicam\files
Add on new project:
Application used to take screenshot from camera
See: \os\petalinux\project-spec\meta-user\recipes-apps\fgrab
Add on new project:
Simple module stab to use audio interface.
See: \os\petalinux\project-spec\meta-user\recipes-modules\te-audio-codec\files
Add on new project:
Simple profile for alias
See: \project-spec\meta-user\recipes-core\base-files\files\profile
Add on new project:
Note: |
No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
|
|