Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

    • Note:

Block Diagram




image link to the generate drawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below



add drawIO object here: Attention if you copy from other page, objects are only linked.

image link to the generate drawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


  1. ...

  2. ...

  3. ...

Initial Delivery State

Storage device name

Content

Notes

..

..

..
OTP Flash areaEmptyNot programmed.


Control Signals

  • Overview of Boot Mode, Reset, Enables,

Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Subsections...

On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Chip/InterfaceICPS7 Peripheral
SPI FlashS25FL127SABMFV10QSPI016 MByte Flash
I2C EEPROM24xx64I2C08 KByte EEPROM
RTC I2CRV-3029I2C0
RTC InterruptRV-3029GPIO - MIO0
User LED
GPIO - MIO7

16 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

RTC I2C


User LED

DesignatorColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenPL pin V18HighLVCMOS33

512 Mbyte DDR3L SDRAM

Power and Power-On Sequence

Ethernet

There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet is available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.

Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.


ETH1ETH2PullupNotes
CTREFJ3.57J3.25
Magnetics center tap voltage
TD+J3.58J3.28on-board
TD-J3.56J3.26on-board
RD+J3.52J3.22on-board
RD-J3.50J3.20on-board
LED1J3.55J3.23on-board
LED2J3.53J3.21on-board
LED3J3.51J3.19on-board
POWERDOWN/INTL21R20on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_NM15R16on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

It is recommended to add IOB TRUE constraint for the MII Interface pins.

When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

Power Consumption

Power Distribution Dependencies


add drawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate drawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Power-On Sequence


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Voltage Monitor Circuit

Power Rails

Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes
VIN1, 3--Input
3.3192, 4-Output

1.8

395-Output







Bank Voltages

Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors


FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM148

500JM14

33JM334

35JM320

35JM222

501JM238

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsReference Document











Recommended Operating Conditions

ParameterMinMaxUnitsReference Document











Physical Dimensions


Variants Currently In Production


Trenz shop TE0xxx overview page
English pageGerman page



Revision History

Hardware Revision History

DateRevisionNotePCNDocumentation Link
-01Prototypes--








Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription


  • change list

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all

  • --


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