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Overview

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

• • Xilinx XA7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: automotive
  • 2 x ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • 16 MByte QSPI Flash memory (with XiP support)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • CAN transceiver (PHY)
  • 12 V power supply with watchdog
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
  • Evenly-spread supply pins for good signal integrity
    
    Other assembly options for cost or performance optimization plus high volume prices available on request.

    Depending on the customer design, additional cooling might be required.

Block Diagram

Main Components

1. 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
3. 100 MBit Ethernet transceiver  DP83848MPHPEP, U3
4. 3.5V to 60V step-down converter with Eco-mode, Texas Instruments TPS54260-Q1, U4
5. Standard Clock Oscillators 25MHz 3.3V, SiTime SiT1618xx, U5
6. 1.5 A Low Dropout Linear Regulator with programmable soft-start, Texas Instruments, TPS74801QRGWRQ1, U6
7. Real Time Clock, Micro Crystal RV-3029-C3, U7
8. 3.5V to 60V step-down converter with Eco-mode, Texas Instruments TPS54260-Q1, U8
9. 3.5V to 60V step-down converter with Eco-mode, Texas Instruments TPS54260-Q1, U9
10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
11. 64 Kbit I2C EEPROM,  24AA64/24LC64/ 24FC64,(24xx64), U11
12. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808Gxx-Q1, U12
13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
14. Standard Clock Oscillators 50MHz 3.3V, SiTime SiT8918xx, U14
15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808Gxx-Q1, U15
16. CAN Tranceiver, Texas Instruments SN65HVD230Q, U16
    
    

Initial Delivery State

Control Signals

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

PS7 UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

Subsections...

On-board Peripherals

16 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided here. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

RTC I2C

EEPROM

LED

512 Mbyte DDR3L SDRAM

The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.

• Part number: NT5CC256M16DP Nanya
• Supply voltage: 1.35V
• Speed: 1600 Mbps
• NOR Flash
• Temperature: 0C~95C

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848-EP provided by Texas Instrument on the board. Datasheet is provided TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

It is recommended to add IOB TRUE constraint for the MII Interface pins.

When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

Clock Source

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Voltage Monitor Circuit

Power Rails

Bank Voltages

Board to Board Connectors

Absolute Maximum Ratings

Technical Specifications

Recommended Operating Conditions

Physical Dimensions

Variants Currently In Production

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History

Date Revision Contributor Description change list -- all --

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