Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0728 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

    • Note:

Block Diagram





Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below





  1. Board to Board Connector, J1-J2-J3
  2. LEDs , D1
  3. CR1220 Backup-Battery holder, B1
  4. SD Card Connector, J10
  5. RJ45 Gigabit Ethernet connector, J7-J8
  6. User push-button, S1
  7.  Jumper, J4
  8. Barrel jack for power supply, J9
  9. Jumper, J11
  10. External connector (VG96) placeholder, J5 / J6

Initial Delivery State

There is no hardware component to be programmed on teh carrier.

Storage device name

Content

Notes





Control Signals

  • Overview of Boot Mode, Reset, Enables,

Boot Process

Signal

DesignatorB2BJumperBoot Mode

Boot_R

J4

J2-11

Open

QSPI

ShortSD Card


Reset Process

There is a user push button which is used for RESET signal.

Signal

DesignatorB2BActive Level

RESET

S1

J2-7

Active High



Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:


B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O48 singel ended, 24 differentialConnected to Bank 13
4 Single endedMIO10-13
CANH , CANL2 single endedMIO8, MIO9
J2

User I/O22 singel ended, 11 differential
38 single endedMIO16-53
SoM Control Signals5RESET, RST_OUT, BOOT_R,
JTAG Interface4TCK , TDO, TDI, TMS

J3


User I/O20 Single ended, 10 differential


Connected to Bank 35
34 single ended, 17 differentialConnected to Bankd 33
Ethernet 14 single ended, 2 differentialETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3
Ethernet 24 single ended, 2 differentialETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3


On-board Connector

B2B ConnectorInterfacesNumber of I/ONotes
J5

User I/O48 singel ended, 24 differentialConnected to Bank 13
34 single ended, 17 differentialConnected to Bank 33
J6

User I/O42 singel ended, 21 differential
27 single endedMIO16... MIO39 + MIO 51-53
4 single endedMIO10-13
SoM Control Signals3RESET, RST_OUT, BOOT_R
JTAG Interface4TCK , TDO, TDI, TMS

CANH , CANL

2 single endedMIO8 , MIO9


JTAG Interface Base

JTAG access to the TE0728 Trenz Module through B2B connector J2. JTAG Programmer TE0790 is provided by Trenz Electronic, More information is available here.

Designator

Connected to

B2B Pin

Note
AMIO52J2-15UART
BMIO53J2-16
CTMSJ2-12JTAG interface signal
DTDIJ2-10JTAG interface signal
FTDOJ2-8JTAG interface signal
HTCKJ2-6JTAG interface signal


JTAG mode

The DIP-switch S2 on JTAG interface is connected to JTAGEN.


S2ONOFFDefaultDescription
1Normal modeAdapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be in OFF state always.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)




On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

SD Card Socket

SignalsConnected toB2BNotes
CD/DAT3MIO45J2-31
CMDMIO41J2-29
CLKMIO40_CLKJ2-34
DAT0MIO42J2-37
DAT1MIO43J2-40
DAT2MIO44J2-32
CDMIO46J2-35
WPMIO47J2-33


RJ45 Connector

Signal ETH1B2BSignal ETH2B2BNotes
ETH1_TD+J3-58ETH2_TD+J3-28Transfer
ETH1_TD-J3-56ETH2_TD-J3-26
ETH1_RD+J3_52ETH2_RD+J3-22Receive
ETH1_RD-J3-50ETH2_RD-J3-20
ETH1_CTREFJ3_57ETH2_CTREFJ3-25
ETH1_LED1J3-55ETH2_LED1J3-23Yellow - Activity
ETH1_LED3J3-51ETH2_LED3J3-19Green - Link


LEDs

DesignatorColorConnected toB2BActive LevelNote
D1-ARedMIO48J2-30Active high
D1-BYellowMIO49J2-38Active high
D1-CGreenMIO50J2-36Active high



Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VIN

TBD*



* TBD - To Be Determined

Power Distribution Dependencies


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Power-On Sequence


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Power Supply


Power Rail Name

B2B Connector

DirectionNotes
VI















Bank Voltages

Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 6 x 6 SoM LSHM B2B Connectors

6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

Absolute Maximum Ratings

Processing System(PS)

SymbolsDescriptionMinMaxUnit
VCCPINTPS internal logic supply voltage-0.51.1V
VCCPAUXPS auxiliary supply voltage-0.52.0V
VCCPLLPS PLL supply-0.52.0V
VCCO_DDRPS DDR I/O supply voltage-0.52.0V
VPREFPS input reference voltage-0.52.0V
VCCO_MIO0PS MIO I/O supply voltage for HR I/O banks-0.53.6V
VCCO_MIO1PS MIO I/O supply voltage for HR I/O banks1.713.45V



Programmable Logic(PL)

SymbolsDescriptionMinMaxUnit
VCCINTPL internal logic supply voltage-0.51.1V
VCCPAUXPL auxiliary supply voltage-0.52.0V
VCCPLLPL PLL supply-0.51.1V
VPREFPL input reference voltage-0.52.0V
VCCOPL supply voltage for HR I/O banks-0.53.6V
VINI/O input voltage for HR I/O banks1.713.45V



Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-40125°CSee Xilinx DS187 datasheet.



Recommended Operating Conditions

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.


ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-65150°CSee Xilinx DS187 datasheet.
CAN Transceiver Temperature-40125°CSee Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory-4085°CSee Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature-4095°C

See Nanya NT5CC256M16CP-DIA datasheet.




Physical Dimensions






Variants Currently In Production


Trenz shop TE0728 overview page
English pageGerman page



Revision History

Hardware Revision History

DateRevisionNotePCNDocumentation Link
-01Prototypes--







Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History


  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription


  • change list

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all

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