Template Revision 2.3
TRM Name always "TE Series Name" +TRM, for example "TE0728 TRM" |
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Table of Contents |
Overview
Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.
Within the complete module only Automotive components are installed.
All this in a compact 6 x 6 cm form factor, at the most competitive price.
Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.
Key Features
- Samtec Tiger Eye Terminal Socket ( 80 pins, 2 rows)
- Micro SD card socket
- 3 User LEDs, Red,Yellow, Green
- Two RJ45 Gigabit Ethernet socket
- Trenz 6x6 module connector strips (3 x Samtec Tiger Eye series connectors)
- Barrel Jack for 12V power supply
- One user push button
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Board to Board Connector, J1-J2-J3
- LEDs , D1
- CR1220 Backup-Battery holder, B1
- SD Card Connector, J10
- RJ45 Gigabit Ethernet connector, J7-J8
- User push-button, S1
- Jumper, J4
- Barrel jack for power supply, J9
- Jumper, J11
- External connector (VG96) placeholder, J5 / J6
Initial Delivery State
There is no hardware component to be programmed on teh carrier.
Storage device name | Content | Notes |
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Control Signals
- Overview of Boot Mode, Reset, Enables,
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Boot Process
Signal | Designator | B2B | Jumper | Boot Mode |
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Boot_R | J4 | J2-11 | Open | QSPI | Short | SD Card |
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Reset Process
There is a user push button which is used for RESET signal.
Signal | Designator | B2B | Active Level |
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RESET | S1 | J2-7 | Active High |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
Number of I/O signals FPGA bank numbers connected to the B2B connectors:
B2B Connector | Interfaces | Number of I/O | Notes |
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J1
| User I/O | 48 singel ended, 24 differential | Connected to Bank 13 | 4 Single ended | MIO10-13 | CANH , CANL | 2 single ended | MIO8, MIO9 | J2
| User I/O | 22 singel ended, 11 differential |
| 38 single ended | MIO16-53 | SoM Control Signals | 5 | RESET, RST_OUT, BOOT_R, | JTAG Interface | 4 | TCK , TDO, TDI, TMS | J3
| User I/O | 20 Single ended, 10 differential
| Connected to Bank 35 | 34 single ended, 17 differential | Connected to Bankd 33 | Ethernet 1 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 | Ethernet 2 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 |
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On-board Connector
B2B Connector | Interfaces | Number of I/O | Notes |
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J5
| User I/O | 48 singel ended, 24 differential | Connected to Bank 13 | 34 single ended, 17 differential | Connected to Bank 33 | J6
| User I/O | 42 singel ended, 21 differential |
| 27 single ended | MIO16... MIO39 + MIO 51-53 | 4 single ended | MIO10-13 | SoM Control Signals | 3 | RESET, RST_OUT, BOOT_R | JTAG Interface | 4 | TCK , TDO, TDI, TMS | CANH , CANL | 2 single ended | MIO8 , MIO9 |
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JTAG Interface Base
JTAG access to the TE0728 Trenz Module through B2B connector J2. JTAG Programmer TE0790 is provided by Trenz Electronic, More information is available here.
Designator | Connected to | B2B Pin | Note |
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A | MIO52 | J2-15 | UART | B | MIO53 | J2-16 |
| C | TMS | J2-12 | JTAG interface signal | D | TDI | J2-10 | JTAG interface signal | F | TDO | J2-8 | JTAG interface signal | H | TCK | J2-6 | JTAG interface signal |
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JTAG mode
The DIP-switch S2 on JTAG interface is connected to JTAGEN.
S2 | ON | OFF | Default | Description |
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1 | Normal mode | Adapter board CPLD update mode | ON | Update Mode JTAG access to SC CPLD only | 2 | Do not use (illegal setting) | Normal mode | OFF | Must be in OFF state always. | 3 | VIO connected to 3.3V | Power VIO from pin header J2 | OFF | User I/O Voltage | 4 | Power 3.3V from USB | Power 3.3V from pin header J2 | OFF | Power on-board peripherals (FTDI chip & SC CPLD, ...) |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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SD Card Socket
VDD for SD card holder is 3.3V.
Signals | Connected to | B2B | Notes |
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CD/DAT3 | MIO45 | J2-31 |
| CMD | MIO41 | J2-29 |
| CLK | MIO40_CLK | J2-34 |
| DAT0 | MIO42 | J2-37 |
| DAT1 | MIO43 | J2-40 |
| DAT2 | MIO44 | J2-32 |
| CD | MIO46 | J2-35 |
| WP | MIO47 | J2-33 |
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RJ45 Connector
Signal ETH1 | B2B | Signal ETH2 | B2B | Notes |
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ETH1_TD+ | J3-58 | ETH2_TD+ | J3-28 | Transfer | ETH1_TD- | J3-56 | ETH2_TD- | J3-26 |
| ETH1_RD+ | J3_52 | ETH2_RD+ | J3-22 | Receive | ETH1_RD- | J3-50 | ETH2_RD- | J3-20 |
| ETH1_CTREF | J3_57 | ETH2_CTREF | J3-25 |
| ETH1_LED1 | J3-55 | ETH2_LED1 | J3-23 | Yellow LED- Activity | ETH1_LED3 | J3-51 | ETH2_LED3 | J3-19 | Green Green- Link |
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Push button
Designator | Connected to | B2B | Active Level | Note |
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S1 | RESET | J2-7 | Active high | General Input RESET |
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LEDs
Designator | Color | Connected to | B2B | Active Level | Note |
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D1-A | Red | MIO48 | J2-30 | Active high |
| D1-B | Yellow | MIO49 | J2-38 | Active high |
| D1-C | Green | MIO50 | J2-36 | Active high |
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Power and Power-On Sequence
Power Supply
Single 12V power supply with minimum current capability of 3.5A is recommended to operate the board.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* | VBATT | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
image link to the generate drawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power-On Sequence
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Supply
Power Rail Name | B2B Connector | Direction | Notes |
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VIN | J1-1, J1-3 | Input |
| VBAT | J2-1 | Input | Battery for RTC | VCCO_13 | J1-39 | Input | Jumper(J11) connects VCCO_13 to 3.3v or 1.8v |
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Bank Voltages
Board to Board Connectors
6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)
Operating Temperature:-55°C ~ 125°C
Current Rating: 2.6A per ContactNumber of Positions: 80
Number of Rows: 2
Absolute Maximum Ratings
Processing System(PS)
Symbols | Description | Min | Max | Unit |
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VCCPINT | PS internal logic supply voltage | -0.5 | 1.1 | V | VCCPAUX | PS auxiliary supply voltage | -0.5 | 2.0 | V | VCCPLL | PS PLL supply | -0.5 | 2.0 | V | VCCO_DDR | PS DDR I/O supply voltage | -0.5 | 2.0 | V | VPREF | PS input reference voltage | -0.5 | 2.0 | V | VCCO_MIO0 | PS MIO I/O supply voltage for HR I/O banks | -0.5 | 3.6 | V | VCCO_MIO1 | PS MIO I/O supply voltage for HR I/O banks | 1.71 | 3.45 | V |
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Programmable Logic(PL)
Symbols | Description | Min | Max | Unit |
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VCCINT | PL internal logic supply voltage | -0.5 | 1.1 | V | VCCPAUX | PL auxiliary supply voltage | -0.5 | 2.0 | V | VCCPLL | PL PLL supply | -0.5 | 1.1 | V | VPREF | PL input reference voltage | -0.5 | 2.0 | V | VCCO | PL supply voltage for HR I/O banks | -0.5 | 3.6 | V | VIN | I/O input voltage for HR I/O banks | 1.71 | 3.45 | V |
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Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. | Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. | I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. | Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. | I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. | Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. | I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. | Storage Temperature | -40 | 125 | °C | See Xilinx DS187 datasheet. |
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Recommended Operating Conditions
Commercial grade: 0°C to +70°C.
Industrial and automotive grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. | Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. | I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. | Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. | I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. | Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. | I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. | Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. | CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. | SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127S datasheet. | DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
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Physical Dimensions
Variants Currently In Production
Revision History
Hardware Revision History
Date | Revision | Note | PCN | Documentation Link |
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- | 01 | Prototypes | - | - |
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Document Change History
- Note this list must be only updated, if the document is online on public doc!
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Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Disclaimer