Design Name always "TE Series Name" + Design name, for example "TEI0006 Test Board"

DateVersionChangesAuthor
2022-04-212.1
  • update to 21.x
TD
2022-02-282.0
  • add yocto to
    • Overview → Key Features
    • Overview → Requirements
    • Design Flow
    • Launch
  • add section 'Software Design - Yocto'
TD
2021-06-151.2
  • table of content view
  • template history
  • placed a horizontal separation line under each chapter heading
  • replaced <design name> by <project folder>
  • changed title-alignment for tables from left to center
  • update 19.x to 20.x
JH,TD
2020-11-241.1
  • add fix table of content
  • add table size as macro
JH
--1.0----


Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):


        Create DrawIO object here: Attention if you copy from other page, use


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • ExampleComment
        12



  • ...

Overview



Notes :

NIOS II Design with SDRAM controller, different sensors and LED sequences.

Refer to http://trenz.org/analogmax-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • Add basic key futures, which can be tested with the design


  • Quartus Prime Lite 21.1
  • NIOS II
  • SPI
  • I2C
  • UART
  • ADC
  • User flash memory
  • SDRAM memory
  • 3-axis accelerometer
  • Temperature sensor
  • Smoke detector
  • User LEDs
  • User buttons

Revision History

Notes :

  • add every update file on the download
  • add design changes on description


DateQuartusProject BuiltAuthorsDescription
2022-04-2121.1 Lite

TEI0010-test_board_noprebuilt-quartus_21.1.0-20220421145917.zip

TEI0010-test_board-quartus_21.1.0-20220421150010.zip

Thomas Dück
  • update to Quartus Prime Lite 21.1
2021-07-0920.1 Lite

TEI0010-test_board_noprebuilt-quartus_20.1.1-20210709102433.zip

TEI0010-test_board-quartus_20.1.1-20210709102350.zip

Thomas Dück
  • update to Quartus Prime Lite 20.1
  • TE scripts update
2020-10-1919.1 Lite

TEI0010-test_board_noprebuilt-quartus_19.1.0-20201019102006.zip

TEI0010-test_board-quartus_19.1.0-20201019101953.zip

Thomas Dück
  • script update
  • bugfixes
2020-05-1319.1 Lite

TEI0010-test_board_noprebuilt-quartus_19.1.0-20200513105940.zip

TEI0010-test_board-quartus_19.1.0-20200513110730.zip

Thomas Dück
  • 19.1 update
2019-11-1118.1

TEI0010-test_board_noprebuilt-quartus_18.1-20191111104210.zip

TEI0010-test_board-quartus_18.1-20191111104330.zip

Thomas Dück
  • create project with TE scripts
  • new board variants
2019-04-1718.1TEI0010-02-08-C8-test_board-quartus_18.1-20190417.zipThomas Dück
  • initial release


Release Notes and Know Issues

Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


IssuesDescriptionWorkaroundTo be fixed version
No known issues---------


Requirements

Software

Notes :

  • list of software which was used to generate the design


SoftwareVersionNote
Quartus Prime Lite21.1needed
NIOS II SBT for Eclipse---optional


Hardware

Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Complete List is available on <project folder>/board_files/*_devices.csv

Design supports following modules:

Module ModelPCB Revision SupportBoard Part Short NameDDRQSPI FlashOthersNotes
TEI0010-02-08-C8*REV0208_C8_8MB8MByte64MBit------

*used as reference

Design supports following carriers:

Carrier ModelNotes
------

*used as reference

Additional HW Requirements:

Additional HardwareNotes
USB cable for JTAG/UARTCheck Carrier Board and Programmer for correct type

*used as reference

Content

Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Intel devices

Design Sources

TypeLocationNotes
Quartus

<project folder>/source_files/quartus

Quartus project will be generated by TE Scripts

Software

<project folder>/source_files/software

Additional software will be generated by TE Scripts


Prebuilt

Notes :

  • prebuilt files
  • Template Table:

    • File

      File-Extension

      Description

      SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
      SRAM Object File*.sofRam configuration file
      Programmer Object File*.pofFPGA configuration file
      JTAG Indirect Configuration file*.jicFlash configuration file
      Raw binary file*.rbfFPGA configuration file
      Diverse Reports---Report files in different formats
      Software-Application-File*.elfSoftware application for NIOS II processor system




File

File-Extension

Description

SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
Programmer Object File*.pofFPGA configuration file
Diverse Reports---Report files in different formats
Software Application File*.elfSoftware application for NIOS II processor system


Download

Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.

Reference Design is available on:

Design Flow



Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.

See also:


The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.

TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win OS and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality

  1. Open create_project_win.cmd/create_project_linux.sh:
    'Create Project' GUI - example
  2. Select Board in "Board selection"
  3. Click on "Create project" button to create project
    1. (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"

Launch



Note:

  • Programming and Startup procedure

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

MAX10 Flash

  1. Connect the Module to USB-Port
  2. Open create_project_win.cmd/create_project_linux.sh
  3. Select correct board in "Board selection"
  4. Click on "Program device" button
    1. if prebuilt files are available: select "Program prebuilt file"
    2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
    3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
  5. Click on "Start program device" button

JTAG

Not used on this example.

Usage

  1. Prepare Hardware like described on section Programming
  2. Connect UART USB (most cases same as JTAG)

UART

  1. Open Serial Console (e.g. PuTTY)
    1. select COM Port

      Win OS: see device manager

      Linux OS: see  dmesg | grep tty  (UART is *USB1)


    2. Speed: 115200
  2. Press reset button
  3. Console output depends on used Software project, see Software Design - SDK#Application

System Design - Quartus



Note:

  • Description of Block Design - Project, Block Design - Platform Desginer, ... Block Design Pictures from Export...

Block Design

The block designs may differ depending on the assembly variant.


Block Design - NIOS_test_board.qsys

Software Design - SDK



Note:
  • optional chapter separate

  • sections for different apps

Application

----------------------------------------------------------

General Example:

hello_tei0006

Hello TEI0006 is a Quartus Hello World example as endless loop instead of one console output.

Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

test_board

Software example to test TEI0010 module.

  • You can toggle between following modes by pressing user button
    1. Spirit level
    2. Winbond SPI flash memory test
    3. Temperature measurement
    4. Smoke detector
    5. ADC - AD5592R


Appx. A: Change History and Legal Notices


Document Change History


To get content of older revision got to "Change History" of this page and select older document revision number.

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateDocument Revision

Authors

Description

  • update to Quartus Prime Lite 21.1
2021-07-09v.8Thomas Dück
  • update to Quartus Prime Lite 20.1
  • document style update
  • script update
2020-10-19v.6Thomas Dück
  • script update
  • bugfixes
2020-05-13v.4Thomas Dück
  • 19.1 release
2019-11-11v.3Thomas Dück
  • change design to TE scripts
  • new variants
2019-04-17v.1Thomas Dück
  • Initial release 18.1
--


all

--


Legal Notices






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