Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template (note: inner scroll ignore/only only with drawIO object):
Create DrawIO object here: Attention if you copy from other page, use
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux
<design name>/os/petalinux
PetaLinux template with current configuration
Additional Sources
Type
Location
Notes
SI5338
<design name>/misc/Si5338
SI5338 Project with current PLL Configuration
Prebuilt
Notes :
prebuilt files
Template Table:
File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIN-File
*.bin
Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image
*.img
Debian Image for SD-Card
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.hdf
Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.hdf
Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Important set new Vivado version link on every Design update of new vivado version!
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" Note: Select correct one, see TE Board Part Files
Create HDF and export to prebuilt folder
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Create Linux (uboot.elf and image.ub) with exported HDF
HDF is exported to "prebuilt\hardware\<short name>" Note: HW Export from Vivado GUI create another path as default workspace.
Use TE Template from /os/petalinux Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable. Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increas image size to A:, see TE0712 Test Board#Config
Add Linux files (uboot.elf and image.ub) to prebuilt folder
"prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>" Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
(not longer needed manually: This will be done with Step 10.a automatically with newer scripts (2017.4.10) ) Generate UBoot SREC:
Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
Create "uboot-dummy" application Note: Use Hello World Example
Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
Press Apply or regenerate project Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
Generate MCS Firmware (optional):
Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
Create "SCU" application Note: Select MCS Microblaze and SCU Application
Select Release Built
Regenerate App
Generate Programming Files with HSI/SDK
Run on Vivado TCL: TE::sw_run_hsi Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk Note: See SDK Projects
Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into "\firmware\microblaze_0\"
(optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into "\firmware\microblaze_mcs_0\"
Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"
Launch
Programming
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BD Pictures from Export...
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Check Module and Carrier TRMs for proper HW configuration before you try any design.
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot Note: Alternative use SDK or setup Flash on Vivado manually optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible
Power on PCB Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR
Boot process takes a while, please wait.
Linux
Note: Linux boot process is slower on Microblaze.
Open Serial Console (e.g. putty)
Speed: 9600
COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console: Note: Wait until Linux boot finished For Linux Login use:
User Name: root
Password: root
You can use Linux shell now.
ETH0 works with udhcpc
Vivado HW Manager:
Note:
Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
add controllable IOs with short notes..
Monitoring:
add short notes for signals which will be monitored only
SI5338_CLK0 Counter:
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
Metadata is only used of compatibility of older exports