Template Revision 2.9

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Cyclone10 LP Reference Kit is the world's first development board with a 55kLE Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.

Refer to http://trenz.org/tei0009-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Barrel Jack, J12
  2. RJ45 socket, J8...9
  3. VGA Socket, J11
  4. Push button(Reset), S7
  5. Grove connector, J5
  6. Under/Over Voltage Protector, U9
  7. 7-segment LED, D11
  8. 1x6 pin header, J4
  9. 1x8 pin header, J2...3
  10. User Red LEDs, D2...9
  11. User Red LEDs, D13...17
  12. Push buttons, S1- S3...6
  13. Red LED (CONF_DONE), D10
  14. PSDRAM memory, U3
  15. SDRAM memory, U10
  16. Voltage Regulator, U5- U7
  17. AD/DA Convertor, U2
  18. Pmod 2x6 SMD host socket, P1...6
  19. Intel Cyclone 10 LP, U1
  20. Config Device, U5
  21. 1x10 pin header, J1
  22. EEEPROM, U15- U18- U20
  23. FTDI FT2232H, U14
  24. Micro USB 2.0 receotacle 90, J10
  25. Push button (RST_GPIO), S2
  26. Oscillator, U22
  27. Ethernet PHY, U17- U19
  28. SPI Flash memory, U12

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

SPI Flash



EEPROM


DDR3 SDRAM


FTDI System Controller CPLD

PSDRAM

Config Device


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

Configuration mode has been set to AS (Active Serial) configuration. 

MODE Signal State

MSEL0MSEL1MSEL2MSEL3Connected to Boot Mode

MSEL[0:3]

0100Bank 6

AS (Active Serial)



RESET pin can be set through the push button S1.

Signal

Connected to Note

RESET

S1 (Push button)Connected to nCONFIG
EXT_RST

J3 (1x8 pin header)

Bank 2



Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 1J1 (Pin header)8 Single ended3.3 V
J2 (Pin header)8 Single ended3.3 V
J4 (Pin header)6 Single ended3.3 V
Bank 2

J3 (Pin header)

1 Single ended3.3 V
P1 (PMod SMD host socket)8 Single ended3.3 V
P2 (PMod SMD host socket)8 Single ended3.3 V
J11 (VGA host Socket)14 Single ended3.3 V
Bank 6J5 (Grove connector)2 Single ended3.3 V
Bank 7P5 (PMod SMD host socket)8 Single ended3.3 V
P6 (PMod SMD host socket)8 Single ended3.3 V
Bank 8P3 (PMod SMD host socket)8 Single ended3.3 V
P4 (PMod SMD host socket)8 Single ended3.3 V


PMod SMD Host Socket

TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP.

DesignatorSignalsConnected to Notes
P1P1_IO1...8Bank 2
P2P2_IO1...8Bank 2
P3P3_IO1...8Bank 8
P4P4_IO1...8Bank 8
P5P5_IO1...8Bank 7
P6P6_IO1...8Bank 7


UART Interface

UART access to TEI0009 is available on 1x8 pin header J2. 

SchematicPin HeaderConnected to Voltage LevelNotes
TXDJ2Bank 13.3 V
RXDJ2Bank 13.3 V


Micro USB2.0 Connector

U14(FTDI FT2232) can be accessed through Micro USB2.0 B Receptacle 90 (J10).

SchematicConnected to Voltage LevelNotes
USB_VBUSGND

D-U14 (FTDI FT2232)3.3 V
D+U14 (FTDI FT2232)3.3 V


RJ45 Connectors

TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively. .

PinSchematicETH1 PinETH2 PinNotes
TD+ETH_TX_PU17- TXPU19- TXP
CTETH_CTREF_TCT--Connected to GND
TD-ETH_TX_NU17- TXMU19- TXM
RD+ETH_RX_PU17- RXPU19- RXP
CTETH_CTREF_RCT--Connected to GND
RD-ETH_RX_NU17- RXMU19- RXM
LED GreenETH_LED0U17- NWAYENU19- NWAYEN
LED YellowETH_LED1U17- SPEEDU19- SPEED


VGA socket Connectors

VGA host socket is connected to Cyclone 10 LP through Bank 2.

SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 2Red channel
VGA_GREENVGA_G0...3Bank 2Green channel
VGA_BLUEVGA_B0...3Bank 2Blue channel
VGA_RGB_HSYNCVGA_HSBank 2Horizontal sync
VGA_RGB_VSYNCVGA_VSBank 2Vertical sync


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
SPI Flash memoryU12
SDRAM memoryU10
PSDRAM memoryU3
7 Segment D11
FTDI FT2232U14
Ethernet PHYU17, U19
Configuration DeviceU5
AD/DA ConverterU2
EEPROMU15, U18, U20
User LEDsD2...D17
OscillatorsU16, U22


Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


MIO PinSchematicU?? PinNotes


























RTC

MIO PinSchematicU? PinNotes










MIO PinI2C AddressDesignatorNotes






EEPROM

MIO PinSchematicU?? PinNotes










MIO PinI2C AddressDesignatorNotes





LEDs

SchematicColorConnected toActive LevelNote
















DDR3 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

Ethernet

BankSignal NameETH1ETH2Signal Description







































































CAN Transceiver

BankSchematicU?? PinNotes

D-Tx
Driver Input

R-Rx
Reciever Output



Clock Sources

DesignatorDescriptionFrequencyNote


MHz


MHz


KHz





Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence




Voltage Monitor Circuit


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Power Rails


Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit




V




V




V




V




V




V




V




V











Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.


Physical Dimensions

PCB thickness: ?? mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

if not available, set.


Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents


DateRevisionChangesDocumentation Link
-







Hardware revision number can be found on the PCB board together with the module model number separated by the dash.


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Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • change list

--

all

  • --


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