Template Revision 2.9
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Cyclone10 LP Reference Kit is the world's first development board with a 55kLE Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.
Refer to http://trenz.org/tei0009-info for the current online version of this manual and other available documentation.
Key Features
Note: 'Key Features' description: Important components and connector or other Features of the module → please sort and indicate assembly options |
- Intel Cyclone 10 LP FPGA 10CL055YU484C8G, 55 kLE in 484-pin
- 16 MBit flash memory (optional up to 32 MBit possible)
- Integrated USB Programmer 2
- Connectors
- 256 MBit (optional up to 512 MBit possible) SDRAM
- 128 MBit (optional up to 512 MBit possible) User Quad-SPI Flash memory
- 64 MBit HyperRAM (optional up to 128 MBit possible)
- 2 x MAC address EEPROM
- 2 x Fast Ethernet PHY (10/100 Mbps)
- 8-channel, 12-bit, configurable ADC / DAC with on-chip reference
- Status LEDs, Power LED
- 13 x User LEDs
- 1 x 7-segment display
- 2 x reset buttons
- 5 x user buttons
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Barrel Jack, J12
- RJ45 socket, J8...9
- VGA Socket, J11
- Push button(Reset), S7
- Grove connector, J5
- Under/Over Voltage Protector, U9
- 7-segment LED, D11
- 1x6 pin header, J4
- 1x8 pin header, J2...3
- User Red LEDs, D2...9
- User Red LEDs, D13...17
- Push buttons, S1- S3...6
- Red LED (CONF_DONE), D10
- PSDRAM memory, U3
- SDRAM memory, U10
- Voltage Regulator, U5- U7
- AD/DA Convertor, U2
- Pmod 2x6 SMD host socket, P1...6
- Intel Cyclone 10 LP, U1
- Config Device, U5
- 1x10 pin header, J1
- EEEPROM, U15- U18- U20
- FTDI FT2232H, U14
- Micro USB 2.0 receotacle 90, J10
- Push button (RST_GPIO), S2
- Oscillator, U22
- Ethernet PHY, U17- U19
- SPI Flash memory, U12
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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SPI Flash |
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| EEPROM |
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| DDR3 SDRAM |
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| FTDI System Controller CPLD |
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| PSDRAM |
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| Config Device |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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Configuration mode has been set to AS (Active Serial) configuration.
MODE Signal State | MSEL0 | MSEL1 | MSEL2 | MSEL3 | Connected to | Boot Mode |
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MSEL[0:3] | 0 | 1 | 0 | 0 | Bank 6 | AS (Active Serial) |
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RESET pin can be set through the push button S1.
Signal | Connected to | Note |
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RESET | S1 (Push button) | Connected to nCONFIG | EXT_RST | J3 (1x8 pin header) Bank 2 |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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I/Os on Pin Headers and Connectors
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | Connector | I/O Signal Count | Voltage Level | Notes |
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Bank 1 | J1 (Pin header) | 8 Single ended | 3.3 V |
| J2 (Pin header) | 8 Single ended | 3.3 V |
| J4 (Pin header) | 6 Single ended | 3.3 V |
| Bank 2 | J3 (Pin header) | 1 Single ended | 3.3 V |
| P1 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| P2 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| J11 (VGA host Socket) | 14 Single ended | 3.3 V |
| Bank 6 | J5 (Grove connector) | 2 Single ended | 3.3 V |
| Bank 7 | P5 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| P6 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| Bank 8 | P3 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| P4 (PMod SMD host socket) | 8 Single ended | 3.3 V |
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PMod SMD Host Socket
TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP.
Designator | Signals | Connected to | Notes |
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P1 | P1_IO1...8 | Bank 2 |
| P2 | P2_IO1...8 | Bank 2 |
| P3 | P3_IO1...8 | Bank 8 |
| P4 | P4_IO1...8 | Bank 8 |
| P5 | P5_IO1...8 | Bank 7 |
| P6 | P6_IO1...8 | Bank 7 |
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UART Interface
UART access to TEI0009 is available on 1x8 pin header J2.
Schematic | Pin Header | Connected to | Voltage Level | Notes |
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TXD | J2 | Bank 1 | 3.3 V |
| RXD | J2 | Bank 1 | 3.3 V |
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Micro USB2.0 Connector
U14(FTDI FT2232) can be accessed through Micro USB2.0 B Receptacle 90 (J10).
Schematic | Connected to | Voltage Level | Notes |
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USB_VBUS | GND |
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| D- | U14 (FTDI FT2232) | 3.3 V |
| D+ | U14 (FTDI FT2232) | 3.3 V |
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RJ45 Connectors
TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively. .
Pin | Schematic | ETH1 Pin | ETH2 Pin | Notes |
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TD+ | ETH_TX_P | U17- TXP | U19- TXP |
| CT | ETH_CTREF_TCT | - | - | Connected to GND | TD- | ETH_TX_N | U17- TXM | U19- TXM |
| RD+ | ETH_RX_P | U17- RXP | U19- RXP |
| CT | ETH_CTREF_RCT | - | - | Connected to GND | RD- | ETH_RX_N | U17- RXM | U19- RXM |
| LED Green | ETH_LED0 | U17- NWAYEN | U19- NWAYEN |
| LED Yellow | ETH_LED1 | U17- SPEED | U19- SPEED |
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VGA socket Connectors
VGA host socket is connected to Cyclone 10 LP through Bank 2.
Schematic | Corresponding Signals | Connected to | Notes |
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VGA_RED | VGA_R0...3 | Bank 2 | Red channel | VGA_GREEN | VGA_G0...3 | Bank 2 | Green channel | VGA_BLUE | VGA_B0...3 | Bank 2 | Blue channel | VGA_RGB_HSYNC | VGA_HS | Bank 2 | Horizontal sync | VGA_RGB_VSYNC | VGA_VS | Bank 2 | Vertical sync |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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SPI Flash memory | U12 |
| SDRAM memory | U10 |
| PSDRAM memory | U3 |
| 7 Segment | D11 |
| FTDI FT2232 | U14 |
| Ethernet PHY | U17, U19 |
| Configuration Device | U5 |
| AD/DA Converter | U2 |
| EEPROM | U15, U18, U20 |
| User LEDs | D2...D17 |
| Oscillators | U16, U22 |
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SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Pin | Schematic | Connected to | Notes |
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CS | F_CS | Bank 7 |
| CLK | F_CLK | Bank 7 |
| IO0...3 | F_IO0...3 | Bank 7 |
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SDRAM Memory
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0009 has 64 Mb volatile , SDRAM IC(U10) for storing user application code and data.
RTC
MIO Pin | Schematic | U? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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EEPROM
MIO Pin | Schematic | U?? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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LEDs
Schematic | Color | Connected to | Active Level | Note |
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Ethernet
Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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CAN Transceiver
Bank | Schematic | U?? Pin | Notes |
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| D-Tx |
| Driver Input |
| R-Rx |
| Reciever Output |
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Clock Sources
Designator | Description | Frequency | Note |
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| MHz |
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| KHz |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Voltage Monitor Circuit
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Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
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Date | Revision | Contributor | Description |
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Disclaimer