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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
Table of contents |
CPLD Device with designator U21: LCMX02-256HC
See Document Change History
| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| C_TCK | in | 30 | 3.3VIN | JTAG B2B |
| C_TDI | in | 32 | 3.3VIN | JTAG B2B |
| C_TDO | out | 1 | 3.3VIN | JTAG B2B |
| C_TMS | in | 29 | 3.3VIN | JTAG B2B |
| EN1 | in | 27 | 3.3VIN | Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback |
| User_LED | out | 4 | 3.3VIN | user defined or status, see LED description |
| N.C. | 5 | 3.3VIN | / currently_not_used | |
| JTAGEN | in | 26 | 3.3VIN | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
| MODE | in | 25 | 3.3VIN | Boot Mode for Zynq/ZynqMP Devices (Flash or SD) |
| MODE0 | out | 12 | 1.8V | ZynqMP Boot Mode Pin 0 |
| MODE1 | out | 13 | 1.8V | ZynqMP Boot Mode Pin 1 |
| MODE2 | out | 14 | 1.8V | ZynqMP Boot Mode Pin 2 |
| MODE3 | out | 16 | 1.8V | ZynqMP Boot Mode Pin 3 |
| NOSEQ | inout | 23 | 3.3VIN | usage CPLD Variant depends |
| PGOOD | out | 28 | 3.3VIN | Module Power Good (only Feedback from EN1). |
| PUDC_B | out | 17 | 1.8V | PUD_C → external pullup |
| TCK | out | 9 | 1.8V | JTAG ZynqMP |
| TDI | out | 8 | 1.8V | JTAG ZynqMP |
| TDO | in | 10 | 1.8V | JTAG ZynqMP |
| TMS | out | 11 | 1.8V | JTAG ZynqMP |
| X0 | in | 20 | VCCO_65 | FPGA IO (FPGA Pin B1) / Enable User LED (negative) |
| X1 | in | 21 | VCCO_65 | FPGA IO (FPGA Pin C1)/ Connect to User LED |
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.
Boot Modes can be selected via B2B Pin Mode. Trenz Electronic provides currently 4 Firmware variants, one for SD/JTAG, one for JTAG/QSPI, one for SD/QSPI and SD/QSPI/JTAG usage.
| Mode | JTAG/QSPI-Variant | SD/JTAG-Variant | SD/QSPI (default Firmware) | SD/QSPI/JTAG |
|---|---|---|---|---|
| low | JTAG | Boot from SD | Boot from SD | JTAG Mode, if NOSEQ* is high otherwise boot from SD |
| high | Boot from Flash | JTAG | Boot from Flash | JTAG Mode, if NOSEQ* is high otherwise boot from Flash |
For other UltraScale+ Boot Modes options custom firmware is needed, see also Table 11.1 Boot Modes from Xilinx UG1085.
A special FSBL is provided on 2017.4 or newer reference designs to write boot image to QSPI with Xilinx tools (Vivado or SDK) on Boot Mode unequal JTAG . |
NOSEQ*: Please check the carrier board documentation, before using the SD/QSPI/JTAG firmware variant on TE0821. In the most cases special carrier CPLD firmware is needed. |
const. 1 → The I/Os will be 3-stated after power-on when PUDC is High.
PGOOD is EN1. There is no additional power management controlled by CPLD.
| LED | Condition |
|---|---|
| Firmware Variant | if X0 is high (default, if FPGA is not programmed) |
| User Defined (X1) | if X0 is low |
*It's recommended to forward this signal to a carrier LED if status check is needed.
| Firmware Variant | Blink sequence | Condition |
|---|---|---|
| QSPI/JTAG | *ooooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
| JTAG/SD | **oooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
| QSPI/SD | ****oooo *****ooo ******** | ****oooo if Boot Mod is QSPI otherwise *****ooo if NOSEQ='1' or ******** if NOSEQ='0' |
| SD/QSPI/JTAG | ***ooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
To get content of older revision got to "Change History" of this page and select older document revision number.
| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
|---|---|---|---|---|---|
| REV01 | REV01 |
| |||
| All |