Template Revision 2.6

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TEI0015 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10.  Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. SMA Connector, J5...6
  2. Amplifier, U12- U14- U6
  3. Series Voltage Reference, U8
  4. Analog to Digital Convertor, U15
  5. Voltage Regulator, U10- U13- U16
  6. Switching Voltage Regulator, U11- U4
  7. Intel® MAX 10, U1
  8. SDRAM Memory, U2
  9. SPI Flash Memory, U5
  10. 12.00 MHz MEMS oscillator, U7
  11. FTDI USB2 to JTAG/UART adapter, U3
  12. User LEDs, D2...9
  13. 4Kb EEPROM, U9
  14. Configuration LED (Red) , D10
  15. Power-on LED (Green), D1
  16. Push button, S1...2
  17. Micro USB2 Receptacle, J9
  18. 1x14 pin header (Not assembled), J2
  19. 1x6 pin header (Not assembled), J4
  20. Jumper, J3
  21. 1x14 pin header (Not assembled), J1

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROM

Programmed

FTDI configuration

SDRAMNot Programmed



Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Reset process must be done by pressing push button S1.

Signal

Push ButtonPin HeaderNote

RESET

S1J2connected to nCONFIG


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
J123.3VDIO0...1
Bank 8J213.3VRESET


FPGA I/O Banks

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI




FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2


41x14 Pin header, J1D2...5
5A2D, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
112MHz Oscillator, U7CLK12M
2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 322SDRAM, U2RAM_ADDR_CMD
Bank 59

1x14 Pin header, J2

DIO6...14
21x14 Pin header, J1DIO0...1
1D12_RDIO12
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
1D11_RDIO11
Bank 8



8User Red LEDs, D2...9LED0...7
6SPI Flash, U5F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn
1Red LED, D10CONF_DONE
6FTDI JTAG/UART Adapter, U3BDBUS0...5
1Push Button, S2USER_BTN


Micro USB2.0 Connector

The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.

PinsConnected toNote
VBUSUSB_VBUSIt is connected to GND
D+

FTDI FT2232H U3,

DP pin


D-

FTDI FT2232H U3,

DM pin



JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4.

JTAG Signal

Pin Header Connector

Note
TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3


JTAG_ENJ4-2


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
SDRAMU2
FTDI FT2232HU3JTAG/UART Adapter
SPI Flash MemoryU5
EEPROMU9
OscillatorU712MHz clock source
ADCU12, U14Analog to Digital Converter
8x User LEDsD2...9Red LEDs


SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable


FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6
ADBUS3TMS

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4user configurable
BDBUS1BDBUS1FPGA bank 8, pin B4user configurable
BDBUS2BDBUS2FPGA bank 8, pin B5user configurable
BDBUS3BDBUS3FPGA bank 8, pin A6user configurable
BDBUS4BDBUS4FPGA bank 8, pin B6user configurable
BDBUS5BDBUS5FPGA bank 8, pin A7user configurable


SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

Signal Schematic NameConnected toNotes
F_CSFPGA bank 8, pin B3chip select
F_CLKFPGA bank 8, pin A3clock
F_DIFPGA bank 8, pin A2data in / out
nSTATUS

FPGA bank 8, pin C4

data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2data in / out


EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

SchematicConnected toNotes

EECS

FTDI U3, Pin EECS
EECLKFTDI U3, Pin EECLK
EEDATAFTDI U3, Pin EEDATA


ADC

The TEI0015 board is equipped with the 18-bit 2MSPS ADC provided by Analog Devices, .

PinsConnected toNotes

IN+

Diff Amplifier U14, VOUT-
IN-Diff Amplifier U14, VOUT+
SDIBank 2, ADC_SDI
SDOBank 2, ADC_SDO
SCKBank 2, ADC_SCK
CNVBank 2, ADC_CNV


LEDs

DesignatorColorConnected toActive LevelNote
D2...9RedLED1...8Active HighUser LEDs
D10RedCONF_DONEActive LowConfiguration DONE LED
D1Green3.3V Active HighAfter power on it will be on


Push Bottuns

DesignatorConnected toFunctionalityNote
S1RESETGeneral reset
S2USER_BTNUser push buttonConnected to Bank 8


Clock Sources

Clock SourceSchematic NameFrequencyNote
Microchip MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3

Connected to FPGA SoC bank 2, pin H6


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommended.

Power Consumption

FPGATypical Current
Intel MAX 10 10M08 FPGA SoCTBD*


* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies




Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the Green LED (D1) will be on.

Power Rails


Connector DesignatorVCC / VCCIO Schematic Name

Voltage

DirectionNotes
J2

VIN5VInput
3.3V3.3VOutput
5V5VOutput

J9

USB_VBUS5VInput


Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 1AVCCIO1A3.3V
Bank 1B

VCCIO1B

3.3V
Bank 2VCCIO23.3V
Bank 3VCCIO33.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V


Bank 8VCCIO83.3V



Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnitReference Document

VIN 

Supply voltage4.755.25V
VCC_ONESupply voltage for core and periphery through on-die voltage
regulator
-0.53.9VIntel MAX 10 datasheet
VCCIO

Supply voltage for input and output buffers

-0.53.9
Intel MAX 10 datasheet
VCCASupply voltage for phase-locked loop (PLL) regulator and ADC-0.53.9
Intel MAX 10 datasheet
V_AN_INAnalog Input Voltage on ADC IC U15 pins–0.35.4VAD4003BCPZ datasheet
V_REFAnalog reference voltage on IC U15-0.36VAD4003BCPZ datasheet

T_STG

Storage Temperature-25+85°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

4.755.25V
VCC_ONE3.1353.456Vsee Intel MAX 10 datasheet
VCCIO3.1353.456Vsee Intel MAX 10 datasheet
VCCA3.1353.456Vsee Intel MAX 10 datasheet
V_AN_IN-0.15.1Vsee AD4003BCPZ datasheet
V_REF2.45.1Vsee AD4003BCPZ datasheet

T_OP

0+70°CW9864G6JT-6 datasheet


Physical Dimensions

Module size: 25 mm × 86.5 mm.  Please download the assembly diagram for exact numbers.

PCB thickness: 1.22 mm.

In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

if not available, set.


Trenz shop TEI0015 overview page
English pageGerman page


Revision History

Hardware Revision History

DateRevisionChangesDocumentation Link
2019-02-1101-REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • change list

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all

  • --


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