Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

Notes :

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...

Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • List of key features of the PCB

Block Diagram




Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below





  1. ANSI/VITA 57.1 compliant FMC LPC connector, J1
  2. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
  3. SFP+ connector, J12
  4. PCIe x1 connector, J3
  5. SATA connector, J31
  6. Trenz Electronic 4 x 5 modules B2B connectors, JB1 ... JB3
  7. RJ45 Gigabit Ethernet connector, J9
  8. 2x Firefly arrangement of connectors, J11, J13, J14, J18
  9. Micro-USB2 connector, J10
  10. FTDI FT2232H USB2 to JTAG,UART/FIFO Bridge, U4
  11. Micro-USB2 connector, J16
  12. MAX10 10M08SAU169C8G CPLD, U11
  13. 6-pin 12V power connector, J15
  14. 6x1 JTAG pin header (not fitted)
  15. 3x1 jumper pin header (select VCCIOA), J4
  16. 3x1 jumper pin header (select VCCA_SD), J7
  17. 2x1 pin header (VBAT), J6
  18. 2x5 1,27mm pitch pin header (PJTAG), J19
  19. Push button, S1
  20. 10x dip switch, S2, S3
  21. DCDC LMZ23605TZ @5.0V (5V0PER), U15
  22. DCDC LMZ23605TZ @5.0V (5V0), U9
  23. DCDC LMZ23605TZ @3.3V(3V3IN), U10
  24. 2x green LED (user), D1, D2
  25. green LED (Power), D3
  26. green LED (Status), D4
  27. SD-Card connector (top loader),
  28. DCDC EN5335QI (FMC_VADJ), U1
  29. DCDC EN6338QI @3.3V (3V3FMC), U14
  30. SDIO Level shifter TXS02612, U3

Initial Delivery State

Storage device name

Content

Notes

FTDI chip configuration EEPROM (93AA56B), U6

Xilinx License

Do not overwrite, see warning in related section
MAX10 System Controller CPLD (10M08SAU169C8G), U14SC CPLD Firmware


Control Signals

  • Overview of Boot Mode, Reset, Enables,

To get started with TEF1002 board, some basic control signals are essential and are described in the following table:

Control signal

Switch / Button / LED / PinSignal Schematic Names

Connected to

Functionality

Notes
FMC_VADJ voltage selectionDIP switches S2-1, S2-2, S2-3VID0 ... VID2SC CPLD U11, pins K6, J5, K5sets adjustable voltage for FMC connectordependens on SC CPLD configuration
JTAG enableDIP switch S2-4JTAGENSC CPLD U11, pin E5

OFF: TEF1002 SC CPLD JTAG enabled,
ON: Module/FMC JTAG enabled

-
Module JTAG selectDIP switch S2-5

M_JTAGEN

B2B JB1, pin 90

When S2-4 ON and S2-6 OFF:

OFF: Module SC CPLD JTAG enabled,

ON: Module SOC JTAG enabled

-
FMC JTAG selectDIP switch S2-6FMC_JTAGSC CPLD U11,L3

When S2-4 ON:

OFF: TEF1002 SC CPLD JTAG enabled,

ON: FMC JTAG enabled

dependens on SC CPLD configuration, only avialiable when 4x5 module installed
Enable module powerDIP switch S2-7CM0SC CPLD U11, M3Module power. Set ON to enable module power. (Power management depends on module. )dependens on SC CPLD configuration, only avialiable when 4x5 module installed
No sequenzingDIP switch S2-8CM1SC CPLD U11, L2Module Power management. Set ON to disable module CPLD power management. Power management depends on module and not all modules support extended power management with CPLD.dependens on SC CPLD configuration, only avialiable when 4x5 module installed
Boot ModeDIP switch S3-1CM2SC CPLD U11, K2

Boot Mode for attached module (Default: OFF for primary SD boot and ON for primary QSPI boot. Depends also on module CPLD firmware).

dependens on SC CPLD configuration, only avialiable when 4x5 module installed
FMC VADJ enableDIP switch S3-2USR0SC CPLD U11, K1

ON: FMC VADJ enable also without installed FMC Card

OFF: FMC_FADJ only enabled when FMC installed.

dependens on SC CPLD configuration, only avialiable when 4x5 module installed
ResetPush button S1BUTTONSC CPLD U11, N6Module Reset, Low active module reset. Pin force Power one reset on FPGA/SoC.dependens on SC CPLD configuration
2x User LEDGreen LEDs D1, D2LED1, LED2SC CPLD U11, J5, K5Depends on User configuration, curenntly both off, if not otherwise programmed.dependens on SC CPLD configuration
Board power indicatorGreen LED D33V3INB2B JB1, pin 14, 16

ON: 3.3V on-board voltage available

-
Board status indicatorsGreen LED D4-SC CPLD U11, pin C2

ON: No failure. For other blinking status of this LED please refer to SC Firmware description.

dependens on SC CPLD configuration
Enable module powerSC CPLD U11, D11EN1B2B JB1, pin 27Module power.  (Power management depends on module. )-
No sequenzingSC CPLD U11, E13NOSEQB2B JB1, pin 8Power management depends on module and not all modules support extended power management with CPLD.-
Boot ModeSC CPLD U11, B11MODEB2B JB1, pin 31Boot Mode for attached module. LOW for primary SD boot and HIGH for primary QSPI boot. (Depends also on module CPLD firmware).-
Module ResetSC CPLD U11, E12RESINB2B JB2, pin 17Module Reset-


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

I/O signals connected to the B2B connector: 

B2B ConnectorInterfacesI/O Signal CountNotes
JB1User IO15 single ended or 7 differentialTEF1002 CPLD


16 single ended or 8 differentialFFA


16 single ended or 8 differentialFFB

MIO/PJTAG/User IO4Pinheader J19

CPLD IO2Module CPLD IO to Carrier CPLD

SD IO6-

UART2-

GbE PHY_MDIO + PHY_COM8 +1-

Module Control5NOSEQ,, EN1, PGOOD, MODE, M_JTAGEN

JB2

User IO12 single ended or 6 differentialLPC FMC

MGTs (RX+TX)4PCIe x1, SFP+, LPC FMC, SATA

MGTCLK

1 differential-

CLK1 differential-

USB2OTG-D_P, OTG-D_N

USB Control3OTG-ID
JB3User IO56 single ended or 28 differential

LPC FMC


CLK2 differentialM2C

JTAG4-


FMC LPC Connector

I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J1:

FMC Connector J2 Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
I/O5628B2B JB2 connectorFMC_VADJpins usable as single ended I/O's or LVDS pairs
126B2B JB3 connectorFMC_VADJ
Multi Gigabit Transceiver-2B2B JB3 connector-RX, TX
Gigabit Transceiver Clock-1B2B JB3 connector-
I²C (SDA, SCL)2-SC CPLD U11, pin F9, J8-FMC I²C Geographical Address pins GA0 and GA1 set to GND.
JTAG4-SC CPLD U11, pin M7, N7, M8, F83.3V-
Clock Input-2B2B JB3 connector-2x reference clock inputs
Control Signals2-SC CPLD U11, pin M5, E9-

'PG_C2M',  'FMC_PRSNT'

Reference voltage (FMC_VREF)----Not Connected.


SFP+ Interface

Connector J12 Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver-2B2B JB3 connector-RX, TX
Control6
SC CPLD U113V3_PERTX_FAULT, TX_DIS, M-DEF0, RS0, RS1, LOS
I²C (SDA, SCL)2-SC CPLD U11, pin F9, J8-MUX via CPLD


Firefly like connectors

Connector J12 Pins and InterfacesI/O Signal CountLVDS-pairs countConnected toVCCIO voltageNotes
Multi Gigabit Transceiver-2B2B JB3 connector-RX, TX
Gigabit Transceiver Clock-1B2B JB3 connector-
I²C (SDA, SCL)2-SC CPLD U11, pin F9, J8-FMC I²C Geographical Address pins GA0 and GA1 set to GND.
JTAG4-SC CPLD U11, pin M7, N7, M8, F83.3V-
Clock Input-2B2B JB3 connector-2x reference clock inputs
Control Signals2-SC CPLD U11, pin M5, E9-

'PG_C2M',  'FMC_PRSNT'

Reference voltage (FMC_VREF)----Not Connected.



microUSB JTAG/UART/FIFO Interface

The microUSB connector provides JTAG access through the carriers USB to JTAG/UART/FIFO bridge. JTAG is routed for MUX and CPLD JTAG access to the CPLD. UART signals are connected to the module B2B connectors. For further description of the JTAG MUX see Dip switches or SC CPLD Firmware.  For non-standard functionalitiers compare on-board Peripherals and datasheet of FTDI FT2232H.

microUSB

RJ45 - Ethernet





On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Subsections...

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies


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Power-On Sequence


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Voltage Monitor Circuit

Power Rails

Bank Voltages

Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsReference Document











Recommended Operating Conditions

ParameterMinMaxUnitsReference Document











Physical Dimensions


Variants Currently In Production


Trenz shop TE0xxx overview page
English pageGerman page



Revision History

Hardware Revision History

DateRevisionNotePCNDocumentation Link
-01Prototypes--








Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription


  • change list

--

all

  • --


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