Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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  width: 100% !important;
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TEF0003 is a FPGA Mezzanine Card (FMC) integrated with an Artix 7 FPGA, 512 Mb Flash Memory. 

Refer to http://trenz.org/tef0003-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups:

  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Coaxial Connectors, J2-5
  2. SPI Flash, U9
  3. Xilinx Artix 7 FPGA, U1
  4. Lattice MachXO FPGA, U15
  5. FMC Adapter, J1
  6. EEPROM, U4
  7. I2C Switches, U2, U17-20
  8. Jumper, J7
  9. Serializer, U5-8
  10. Connector Header, J8
  11. Oscillator 25MHz, U11
  12. Programmable Clock Generator, U10
  13. FMC Adapter, J6

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

SPI Flash

Not programmed 


EEPROMNot Programmed 


Clock GeneratorProgrammed


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.


MODE Signal State M[2:0]

Boot ModeNote

110

Master SPI

It is Fixed



Signal

DescriptionNote

PRSNT_TOP

Lattice MachXO Configuration Pin


PROG_BArtix 7 Configuration PinPulled up to 1.8


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

FMC Connectors

FPGA bank number and number of I/O signals connected to the FMC Connectors J1 and J6 which are located on top and bottom of the board.

FPGAFPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Artix 7, U116J1B68 Single Ended, 34 Differential1.8V
35J6B68 Single Ended, 34 Differential1.8V
Lattice MachXO, U0J1F4 Single Ended 3.3VCPLD
0J6F4 Single Ended 3.3VCPLD


Coaxial Connectors

DesignatorSchematicConnected toNotes
J2GA_OUTSerializer, U5
J3GB_OUTSerializer, U6
J4GC_OUTSerializer, U7
J5GD_OUTSerializer, U8



JTAG Interface

The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the MachXO is available through FMC Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.

JTAG Signal

B2B Connector

Notes
FMC_TMSJ6F-TCK
FMC_TDI_TOPJ6F-J1-TDI
FMC_TDO_TOPJ6F-TDO
FMC_TCK

J6F-TCK


JTAGENPulled down



JTAG Signal

Connected to

Note
TMS

Lattice MachXO, U15

BankArtix 7 FPGA, U1

Bank 2

Bank 0

TDI

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

TDO

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

TCK

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

INIT

Artix 7 FPGA, U1

Pulled up to 1.8


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
SPI FlashU9
EEPROMU4
OscillatorsU11
Programmable Clock GeneratorU10


Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

TEF0003 is equipped with a 512Mb Serial NOR Flash (x1/x2/x4) which is provided to store an application in the SPI Flash memory in order to boot the module. The SPI Flash data is connected to Artix 7 via FPGA Bank 14.

SchematicU9 PinNotes
SPI-CSCS
SPI-CLKCLK
SPI-DQODI/IO0
SPI_DQ3HOLD/IO3
SPI-DQ2WP/IO2
SPI-DQ1DO/IO1
1.8VVCC


EEPROM

A microchip serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector J1 (SCL, SDA).

U4 PinFMC Pcam AdapterSchematicNotes
SCLJ1F-SCLFMC_SCL
SDAJ1F-SDAFMC_SDA
A0J1F-GA0GA0
A1J1F-GA1GA1
A2--Pulled Low
WP--Pulled Low



I2C AddressDesignatorNotes
0xA0U4Write operations are enabled 


Clock Sources

DesignatorDescriptionFrequencyNote
U11Oscillator25.00  MHz
U10Programmable Clock GeneratorVariable


Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J8.  The I2C Address is 0x69.

Si5345A Pin
Signal Name / Description
Connected ToDirectionNote

IN0

Reference input clock.

U11Input25.00 MHz oscillator, SiT8008BI
IN1FMCT_GBTCLK0J6EInputFMC Pcam Adapter
IN2FMCT_GBTCLK1J6EInputFMC Pcam Adapter
IN3FMCT_CLK0J6EInputFMC Pcam Adapter

XAXB

-

GNDInput54.00 MHz CX3225SB
SCLKPLL_SCLJ8, U20InputEEPROM
SDAPLL_SDAJ8, U20InputEEPROM
OUT0

GA_PCLK

U5/U1Output

FPGA bank 15

OUT1GB_PCLKU6/U1Output

FPGA bank 15

OUT2GC_PCLKU7/U1Output

FPGA bank 15

OUT3GD_PCLKU8/U1Output

FPGA bank 15

OUT4CLK4_PU1HOutput
OUT5GBTCLK0J1E/J6EOutput
OUT6

GBTCLK1

J1E/J6E

Output


OUT7GBTCLK0J1EOutput
OUT8/OUT9CLK8/CLK9Pulled lowOutput


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
3P3VTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence




Power Rails

Power Rail Name

FMC  Adapter J1G Pin

FMC Adapter J6G Pin

DirectionNotes
12VC35, C37C35, C37Input
3P3VAUXD32D32Input
3P3VD36, D38, D40, C39D36, D38, D40, C39Input

VREFA

H1H1Input
VREFBK1K1Input
VIOBJ39, K40J39, K40Input
VADJH40, G39, F40, E39H40, G39, F40, E39Input


Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 13VCCO_131.8 V
Bank 14VCCO_141.8 V
Bank 15

VCCO_15

1.8 V
Bank 16VCCO_16VADJ1.8 V
Bank 34VCCO_341.8 V
Bank 35VCCO_35VADJ1.8 V
Bank 0VCCO_01.8 V



Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
3P3VInput Supply Voltage-0.53.75V
T_STGStorage Temperature-4085°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
3P3V2.3753.465V
T_OPR-4085°CSee MT25QU512ABB8E12-0SIT (U9)  datasheet.


Physical Dimensions

PCB thickness: 1.56 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .




Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TEF0003 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
2017-06-27REV01

Initial Release

REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • Initial Release

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all

  • --


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