Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TEF0003 is A FPGA Mezzanine Card (FMC) integrated with a Artix 7.
Refer to http://trenz.org/tef0003-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups: - FPGA/Module
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- FPGA: Xilinx Artix 7 (XC7A100T)
- Package: FGG484 (Compatible with
- Speed: -1 (Slowest)
- Temperature: Industrial Grade (–40°C to +100°C)
- RAM/Storage:
- 1x NOR SPI FLASH (128M x 4)
- 1x EEPROM (16K x 8)
- On Board:
- 4x Deserializer IC (3.12 Gbps)
- 4x I2C and SMBus I/O Expander
- 1x Programable Clock Generator
- 1x Clock Generator
- Interface:
- 2x VITA 57 SEAM/SEAF Series system
- 4x Coaxial connectors
- Power:
- 4x Voltage Regulators
- 3.3 Supply Voltage
- Dimension: 72 mm x 65 mm
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Coaxial Connectors, J2-5
- SPI Flash, U9
- Xilinx Artix 7 FPGA, U1
- Lattice MachXO FPGA, U15
- FMC Pcam Adapter, J1
- EEPROM, U4
- I2C Switches, U2, U17-20
- Jumper, J7
- Serializer, U5-8
- Connector Header, J8
- Oscillator 25MHz, U11
- Programmable Clock Generator, U10
- FMC Pcam Adapter, J6
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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SPI Flash | Not programmed |
| EEPROM | Not Programmed |
| Clock Generator | Programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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MODE Signal State M[2:0] | Boot Mode | Note |
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110 | Master SPI | It is Fixed |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA | FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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Artix 7, U1 | 16 | J1B | 68 Single Ended, 34 | 1.8V |
| 35 | J6B | 68 Single Ended, 34 | 1.8V |
| Lattice MachXO, U | 0 | J1F | 4 Single Ended | 3.3V |
| 0 | J6F | 4 Single Ended | 3.3V |
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JTAG Interface
JTAG access to the TEF0003 FMC through FMC Pcam Adapter J6.
JTAG Signal | B2B Connector |
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FMC_TMS | J6F-TCK | FMC_TDI_TOP | J6F-J1-TDI | FMC_TDO_TOP | J6F-TDO | FMC_TCK | J6F-TCK | JTAGEN | J7 |
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MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
TEF0003 is equipped with a 512Mb Serial NOR Flash (x1/x2/x4) which is provided to store an application on the SPI Flash memory in order to boot the module. The SPI Flash data is connected to Artix 7 FPGBA Bank 14.
Schematic | U11 Pin | Notes |
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SPI-CS | CS |
| SPI-CLK | CLK |
| SPI-DQO | DI/IO0 |
| SPI_DQ3 | HOLD/IO3 |
| SPI-DQ2 | WP/IO2 |
| SPI-DQ1 | DO/IO1 |
| 1.8V | VCC |
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EEPROM
A Microchip 24LC128-I/LC serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector J1 (SCL, SDA).
FMC Pcam Adapter | Schematic | U4 Pin | Notes |
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J1F-SCL | FMC_SCL | SCL |
| J1F-SDA | FMC_SDA | SDA |
| J1F-GA0 | GA0 | A0 |
| J1F-GA1 | GA1 | A1 |
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I2C Address | Designator | Notes |
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0x50 | U4 |
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Clock Sources
Designator | Description | Frequency | Note |
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U4 | Oscillator, 25 MHz | MHz |
| U10 | Programmable Clock Generator | MHz |
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Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator on-board (U10) to generate reference clocks for the module. Programming can be done using I2C via PIN header J8. The I2C Address is 0x69.
Si5345A Pin
| Signal Name / Description
| Connected To | Direction | Note |
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IN0 | Reference input clock. | U11 | Input | 25.00 MHz oscillator, SiT8008BI | IN1 | FMCT_GBTCLK0 | J6E | Input | FMC Pcam Adapter | IN2 | FMCT_GBTCLK1 | J6E | Input | FMC Pcam Adapter | IN3 | FMCT_CLK0 | J6E | Input | FMC Pcam Adapter | XAXB | - | GND | Input | 54.0000 MHz XTAL CX3225SB | SCLK | PLL_SCL | J8, U20 | Input | EEPROM Programming | SDA | PLL_SDA | J8, U20 | Input | EEPROM Programming | OUT0 | GA_PCLK | U5/U1 | Output | FPGA bank 15 | OUT1 | GB_PCLK | U6/U1 | Output | FPGA bank 15 | OUT2 | GC_PCLK | U7/U1 | Output | FPGA bank 15 | OUT3 | GD_PCLK | U8/U1 | Output | FPGA bank 15 | OUT4 | CLK4_P | U1H | Output |
| OUT5 | GBTCLK0 | J1E/J6E | Output |
| OUT6 | GBTCLK1 | J1E/J6E | Output |
| OUT7 | GBTCLK0 | J1E | Output |
| OUT8 | CLK8 | Not Conneted | Output | Not Used | OUT9 | CLK9 | Not Conneted | Output | Not Used |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Power Rails
Power Rail Name | FMC Pcam Adapter J1G | FMC Pcam Adapter J6G | Direction | Notes |
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12V | C35, C37 | C35, C37 | Input |
| 3P3VAUX | D32 | D32 | Input |
| 3P3V | D36, D38, D40, C39 | D36, D38, D40, C39 | Input |
| VREFA | H1 | H1 | Input |
| VREFB | K1 | K1 | Input |
| VIOB | J39, K40 | J39, K40 | Input |
| VADJ | H40, G39, F40, E39 | H40, G39, F40, E39 | Input |
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Bank Voltages
| Schematic Name | | Notes |
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Bank 13 | VCCO_13 | 1.8 V |
| Bank 14 | VCCO_14 | 1.8 V |
| Bank 15 | VCCO_15 | 1.8 V |
| Bank 16 | VCCO_16 | VADJ |
| Bank 34 | VCCO_34 | 1.8 V |
| Bank 34 | VCCO_35 | VADJ |
| Bank 0 | VCCO_0 | 1.8 V |
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Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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12V | Input Supply Voltage | -12 | 12 | V | T_STG | Storage Temperature | -40 | 85 | °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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12V | 12 | 12 | V | See ???? datasheets. | T_OPR | -40 | 85 | °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: 1.54 mm.
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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2017-06-27 | REV01 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Revision | Contributor | Description |
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Disclaimer