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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware



Table of contents

Overview

CPLD Device with designator U5: LCMX02-1200HC. CC703S is minimum startup design.

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
ACBUS4 141 / currently_not_used
ACBUS5 140 / currently_not_used
ADBUS4 143 / currently_not_used
ADBUS7 142 / currently_not_used
BCBUS0 122 / currently_not_used
BCBUS1 121 / currently_not_used
BDBUS2 133 / currently_not_used
BDBUS3 132 / currently_not_used
BDBUS4 128 / currently_not_used
BDBUS5 127 / currently_not_used
BDBUS6 126 / currently_not_used
BDBUS7 125 / currently_not_used
CM0in76DIP-S2 / used as JTAG Selection
CM1in75DIP-S1 / used to disable SD_CD-PIN forwarding (To work with PCB REV02,03,03)
E_SD_CMD 110 / currently_not_used
E_SD_DAT0 106 / currently_not_used
E_SD_DAT1 107 / currently_not_used
E_SD_DAT2 112 / currently_not_used
E_SD_DAT3 111 / currently_not_used
E_SD_SCLK 

109

/ currently_not_used
EN1out81B2B Power Enable
FL_0inout28 LED (D3-red) / Status  / not connected on REV02,REV03,REV04
FL_1inout27LED (D4-green) / Status / not connected on REV02,REV03,REV04
FT_B_RXout138FTDI UART
FT_B_TX / BDBUS0in139FTDI UART
JTAGEN 120Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3
M_TCKin131JTAG from/to FTDI
M_TDIin136JTAG from/to FTDI
M_TDOout137JTAG from/to FTDI
M_TMSin130JTAG from/to FTDI
MIO0in94DIP-S4 and B2B Pin / used as Boot Mode
MIO10 98 / currently_not_used
MIO11 97 / currently_not_used
MIO12in100B2B-Module UART2 TX
MIO13out99B2B-Module UART2 RX
MIO14out105B2B-Module UART RX
MIO15in95B2B-Module UART TX
MIO9 out96 SD_CD / not usable as SD_CD on REV02,REV03,REV04
MODEout83Boot Mode Pin. Switch Boot mode of Module (depends on module)
NOSEQ inout78Add Pullup only / currently_not_used
PGOOD inout82Add Pullup used for Status / currently_not_used
PHY_LED1 out86 Status / currently_not_used
PHY_LED1R out92 Status / currently_not_used
PHY_LED2 out85 Status currently_not_used
PHY_LED2R out91 Status / currently_not_used
PROGMODEout104Enable B2B Module JTAG access to CPLD for Firmware update
RESINout119Module Reset Pin on B2B connector
S1in114Push Button / Used as module Reset
SD_CD in93Forward to MIO 9 / not connected on REV02,REV03,REV04
SD_SEL out113set to GND / currently_not_used
TCK_Bout1JTAG from/to Module
TDI_Bout3JTAG from/to Module
TDO_B / C_TDOin2JTAG from/to Module
TMS_Bout4JTAG from/to Module
ULED1 / LED1out117LED (D1-red) / UART Monitoring
ULED2 / LED2out115LED /D2-green) / UART Monitoring
USB_OC 73 / currently_not_used
X0 39 / currently_not_used
X1 38 / currently_not_used
X10 49 / currently_not_used
X11 50 / currently_not_used
X12 52 / currently_not_used
X13 54 / currently_not_used
X14 55 / currently_not_used
X15 56 / currently_not_used
X16in59UART2 on VG connector J2
X17out60UART2 on VG connector J2
X2 40 / currently_not_used
X3 41 / currently_not_used
X4 42 / currently_not_used
X5 43 / currently_not_used
X6 44 / currently_not_used
X7 45 / currently_not_used
X8 47 / currently_not_used
X9 48 / currently_not_used

Functional Description

JTAG

JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module).

TE0703 CPLD can be select with JTAGEN (DIP-S2-3).

Module FPGA/CPLD access can be switched with PROGMODE which is driven by CMD0 (DIP-S2-2).CMD0 is pulled up with CPLD.

S2-2S2-3PROGMODEJTAGENDescription
OFFOFF11Access to TE0703 CPLD
OFFON10Access to CPLD of B2B Module
ONOFF01Access to TE0703 CPLD
ONON00Access to FPGA of B2B Module

Note: LED1,2,3,4 are on and PHY LEDs blink slow, if S2-2 is set to OFF.

Power

EN1 is set to one.

NOSEQ and PGOOD pulled up to VDD.

Reset

RESIN is driven by S1 (Push Button). Button is debounced.

Boot Mode

MODE Pin is sourced by MIO. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP.

S2-4MIO0Description
ON0def. SD-CARD Boot (for Zynq Modules), PHY LEDs glow orange
OFF1def. QSPI-Flash, PHY LEDs glow green

UART

Primary UART:

MIO14 is driven by BDBUS0 (FTDI RX).

BDBUS1 (FTDI TX) is driven by MIO15 .

Secondary UART:

MIO13 is driven by X16.

X17 is driven by MIO12.

SD

SD selection is set to GND (SD Card slot).

MIO9 is SD_CD and CM1(S2-1).Is S2-1 is ON, MIO9 is GND else status depends on SD_CD .

Note: PCB REV02,REV03,REV04 has no SD, set S2-1 to ON

LED

LED Priority is order of the description

LEDPrio 0: PowerPrio 1: Modul CPLD access*Prio 2
LED1 (D1-red)Blink, if Power Good is lowONFTDI UART RX
LED2 (D2-green)Blink, if Power Good is lowONFTDI UART TX
LED3 (D3-red)Blink, if Power Good is lowONUser defined with B2B Pin JB2-99
LED4 (D4-green)Blink, if Power Good is lowONUser defined with B2B Pin JB2-90
PHY LEDs (green/orange)Blink orange, if Power Good is lowBlink Green and orangeGreen: Boot Mode set  to QSPI, Orange: Boot Mode set to SD

*Attention: LED1,2,3,4 are on, if S2-2 is set to OFF. If S2-3 is OFF, TE0703 is in chain!

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription


 

REV02

REV02*,REV03*,REV04*,REV05
*some IOs are not connected
*SD_CD not available, set S2-1 to on


REV 02 finished
2016-04-11

v.1

REV02

REV02*,REV03*,REV04*,REV05
*some unused IOs are not connected
*SD_CD not available, set S2-1 to on


Initial release
 All  

 

Appx. B: Legal Notices