• Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

DateVersionChangesAuthor

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Perihery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro



Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.

Overview


The Trenz Electronic TEI0022 is a SoC board based on Intel Cyclone V FPGA, an Ethernet PHY, one GByte DDR3 SDRAM per HPS and FPGA and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.

Refer to http://trenz.org/tei0022-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


  • SoC FPGA
    • Intel Cyclone V (5CSEMA5F31C8N)
    • Package: FBGA 896 pins
    • Speed Grade: 8
    • Temperature: Commercial (Tj = 0 °C to 85 °C)
  • RAM/Storage
    • 1 GByte DDR3 SDRAM for HPS
    • 1 GByte DDR3 SDRAM for FPGA
    • 32 MByte SPI for HPS
    • 32 MByte SPI for FPGA
  • On Board
    • up to 7 x SMA Connector
    • Temperature Sensor
    • Intel MAX10 for board management
  • Interface
    • LPC FMC Connector
    • 4 x Pmod Connector
    • JTAG 
    • UART via micro USB B Connector (for FPGA)
    • UART via micro USB B Connector (for HPS)
    • 4 x USB 2.0 Host
    • Ethernet via RJ45 Connector
    • SD Card
    • HDMI
  • Power
    • 12 V Input supply voltage
  • Dimension
    • 160 mm x 130 mm

Block Diagram

add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Intel Cyclone V, U10
  2. DDR3 SDRAM, U26...27
  3. DDR3 SDRAM, U28...29
  4. FMC, J4
  5. Pmod, P1...4
  6. SD Card Connector, J3
  7. Ethernet PHY, U1
  8. RJ45 Connector, J1
  9. USB PHY, U8
  10. USB HUB, U33
  11. USB Connector, J2, J12
  12. HDMI Transmitter, U23
  13. HDMI Connector, J11
  14. Intel MAX10, U41
  15. Micro USB to UART Interface, J5, U30
  16. USB to JTAG , U21
  17. Micro USB JTAG and UART, J13
  18. SMA Connector
  19. Push Button, S1, S3...5
  20. LED
  21. 4-Bit DIP Switch, S2, S7...8
  22. 12 V Power Jack, J6
  23. Clock Generator, U48
  24. Programmable Clock Generator, U3
  25. QSPI - FPGA PS, U6
  26. QSPI - FPGA PL, U15
  27. Temperature Sensor, U16
  28. EEPROM, U38

Initial Delivery State


Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



Storage device name

Content

Notes

HPS SPI Flash (U6)

Not programmed

HPS Configuration

FPGA SPI Flash (U15)Not programmedFPGA Configuration
MAC EEPROM (U38)

MAC programmed, otherwise not programmed

Ethernet MAC

FTDI EEPROM (U31)ProgrammedFTDI Functionality
Programmable Clock Generator Si5338 (U3)Programmed, CLK0 - 50M, CLK1 - 50M, CLK2 - 25M, CLK3 - 50M--


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

Boot Mode must be set using DIP Switch S7 on the module TEI0022. Please note that the DIP Switch is active low.

MODE Signal StateBoot ModeNotes
S7-1 (BOOTSEL0)S7-2 (BOOTSEL1)

FPGA

ON

ON--
SD CardONOFF--
QSPI flashOFFOFF--



Reset

ButtonNotes

HPS cold reset

S1--
HPS warm resetS3--
FPGA resetS4--


Signals, Interfaces and Pins



For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

  • Table with all connectors and Designtor
  • List of different interfaces per connector
  • IO CNT (for FPGA IOs where functionality can be changed by customer)


FMC LPC Connector

The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.

The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

FMC SignalIntel Cyclone V DirectionI/O Signal Count (Single Ended/Differential)Voltage LevelNotes
LA0...1RX4 / 2FMC_VADJVoltage level as visible in table Intel Cyclone V SoC bank voltages.
LA3, LA5, LA7, ..., LA33RX32 / 16FMC_VADJVoltage level as visible in table Intel Cyclone V SoC bank voltages.
LA2, LA4, LA6, ..., LA32TX32 / 16FMC_VADJVoltage level as visible in table Intel Cyclone V SoC bank voltages.
CLK0...1RX4 / 2FMC_VADJVoltage level as visible in table Intel Cyclone V SoC bank voltages.


The FMC connector provides further interfaces like JTAG and I²C:

InterfaceI/O Signal CountPin schematic Names / FMC PinsConnected toNotes
JTAG5

FMC_TCK, Pin J4-D29

FMC_TMS, Pin J4-D33

FMC_TDI, Pin J4-D30

FMC_TDO, Pin J4-D31

FMC_TRST#, Pin J4-D34

Intel MAX10 U41, Bank 3VCCIO: +3.3V
I2C2

FMC_SCL, Pin J4-C30

FMC_SDA, Pin J4-C31

Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7AI2C-lines pulled-up to +3.3V
Control Lines2

FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V)

FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)

Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B / 7C

'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier


Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

VCCIO Schematic NameFMC Connector J4 PinsNotes
+12.0V_FMCC35/C37extern 12 V power supply
+3.3V_FMCD36/D38/D40/C393.3 V peripheral supply voltage
+3.3VD323.3 V peripheral supply voltage
FMC_VADJH40/G39adjustable FMC VCCIO voltage, supplied by DC-DC converter U43
FMC_VREF_A_M2CH1adjustable reference voltage


Pmod Connector

The TEI0022 board offers four Pmod (2x6 pins, SMD) connectors which provides as a standard modular interface single ended I/O pins for use with extension modules.

Following table gives an overview of the Pmod connectors and the signals routed to the attached Intel Cyclone V (U10):

Pmod Connector P1 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P0_IO1Pin AD9--
2P0_IO2Pin AD11--
3P0_IO3Pin AD12--
4P0_IO4Pin AC12--
7P0_IO5Pin AC9--
8P0_IO6Pin AD10--
9P0_IO7Pin AA12--
10P0_IO8Pin AB12--
Pmod Connector P2 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P1_IO1Pin AG2--
2P1_IO2Pin AF4--
3P1_IO3Pin AF8--
4P1_IO4Pin AD7--
7P1_IO5Pin AG1--
8P1_IO6Pin AF5--
9P1_IO7Pin AE7--
10P1_IO8Pin AE9--
Pmod Connector P3 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P2_IO1Pin AH5--
2P2_IO2Pin AH3--
3P2_IO3Pin AJ2--
4P2_IO4Pin AG3--
7P2_IO5Pin AG5--
8P2_IO6Pin AH4--
9P2_IO7Pin AH2--
10P2_IO8Pin AJ1--
Pmod Connector P4 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P3_IO1Pin AE12--
2P3_IO2Pin AF9--
3P3_IO3Pin AG8--
4P3_IO4Pin AG6--
7P3_IO5Pin AE11--
8P3_IO6Pin AF10--
9P3_IO7Pin AG7--
10P3_IO8Pin AF6--


SMA Connector

The TEI0022 board offers up to seven SMA connectors for trigger and clock input and output.

SMA Connector

Signal Schematic Names

Connected to

Notes
J7SMA_CLK_OUT_pClock Generator U3, Pin 22Assembly option
J10SMA_CLK_OUT_nClock Generator U3, Pin 21Assembly option
J8TRIGGER_OUTPUTIntel Cyclone V U10, Pin AE29--
J9TRIGGER_INPUTIntel Cyclone V U10, Pin AA26--

J15

EXT_CLK_INPUTIntel Cyclone V U10, Pin Y26--
J17CLK_INPUTIntel Cyclone V U10, Pin AD29--
J18SMA_CLK_INClock Generator U3, Pin 1

Assembly option


FAN Connector

The TEI0022 board offers a FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.

Connector

Signal Schematic Names

Connected to

Notes
2-Pin FAN Connector J16, 5 V or 12 V power supply depending on R270/271 with BTS4141N High Side Switch U55

FAN_EN,

(High Side Switch U55, Pin 3)

Intel MAX10 U41, Pin D13Intel Cyclone V cooling FAN


Micro USB Connector (JTAG)

According to the JTAGEN and JTAGSEL[1..0] pins the management controller Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.

JTAG access is controlled by the DIP switches S7 and S8 on the module TEI0022. Please note that the DIP Switches are active low.

JTAG selectionJTAG Signal StateNote

S7-3 (JTAGSEL0)

S7-4 (JTAGSEL1)

S8-4 (JTAGEN)

XXONIntel MAX10--
ONONOFFIntel Cyclone V HPS--
ONOFFOFFIntel Cyclone V FPGA--
OFFONOFFFMC--






Micro USB Connector (UART)

A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.

USB Connector

On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12).

HDMI Connector

The TEI0022 provides an HDMI Connector J11.

SD Card Connector

SD Card connector J3 is connected to the Intel Cyclone V U10.

RJ45 Connector

The board TEI0022 provides an ethernet interface via the RJ45 connector J1.

I2C

The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is used to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devices. Via assembly option, it is possible to connect bus two to bus three.

BusI2C DeviceDesignatorI2C AddressSchematic Names of I2C Bus LinesNotes
HPS I2CTemperature SensorU160x4AHPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CProgrammable Clock GeneratorU30x70HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CEEPROMU380x50HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HDMI I2CHDMIU230x72HDMI_I2C_SCL / _I2C_SDA3.3 V reference voltage
HPS FMC I2CFMCJ40x50FMC_SCL / FMC_SDA3.3 V reference voltage






On-board Peripherals



Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/InterfaceDesignatorConnected ToNotes
ETH PHYU10
  • B2B connector J1
  • SoC MIO
Gigabit ETH PHY



For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals


Chip/InterfaceDesignatorNotes
System Controller Intel MAX10U41--
Intel Cyclone VU10--
DDR3 SDRAMU26...29--
Gigabit Ethernet PHYU1--
High-Speed USB ULPI PHYU8--
4-Port USB 2.0 HubU33--
HDMI TransmitterU23--
FTDI (JTAG)U21--
FTDI (UART)U30--
DIP-SwitchesS2, S7...8--
ButtonsS1, S3...5

--

On-Board LEDsD1...15, D17...23, D25--
Temperature SensorU16--
QSPIU6, U15--
EEPROMU31, U38--
Clock SourcesU32, U34, U48--
Programmable Clock GeneratorU3--
Power MonitoringU54--


System Controller Intel MAX 10

The TEI0022 is equipped with an Intel MAX 10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.

Intel Cyclone V

The Intel Cyclone V device used at the TEI0022 board is a SoC with integrated ARM-based HPS. The 5CSEMA5F31C8N version delivers one hard memory controller, 80K logic elements in an FineLineBGA (FBGA) with 896 pins for the commercial temperature range of TJ = 0...85 °C with speed grade eight.

DDR3 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA (U26, U27) and HPS (U28, U29) for storing user application code and data.

  • Part number: IS43TR16256BL-125KBLI
  • Supply voltage: 1.5 V
  • Speed: TBD
  • Temperature: TC = -40 °C up to 95 °C

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U48).

BankSignal NameSignal Description
7BETH_TXCKRGMII Transmit Reference Clock
7BETH_TXD0RGMII Transmit Data 0
7BETH_TXD1RGMII Transmit Data 1
7BETH_TXD2RGMII Transmit Data 2
7BETH_TXD3RGMII Transmit Data 3
7B

ETH_TXCTL

RGMII Transmit Control
7BETH_RXCKRGMII Receive Reference Clock
7BETH_RXD0RGMII Receive Data 0
7BETH_RXD1RGMII Receive Data 1
7BETH_RXD2RGMII Receive Data 2
7BETH_RXD3RGMII Receive Data 3
7B

ETH_RXCTL

RGMII Receive Control
7CETH_RSTReset
7BETH_MDCManagement Data Clock
7BETH_MDIOManagement Data I/O
7BPHY_INTInterrupt


High-Speed USB ULPI PHY

USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).

PHY PinConnected toNotes
ULPIIntel Cyclone V HPS (U10)--
REFCLK24 MHz from on board oscillator (U34)--
REFSEL[0..2]High (3.3 V)--
RESETBIntel Cyclone V HPS (U10) and Intel MAX 10 (U41)--
DP, DM4-port USB 2.0 Hub (U33)--
CPENNot Connected.--
VBUSPull-up to 5 V.--
IDNot Connected.--


4-Port USB 2.0 Hub

On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12). The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.

HDMI Transmitter

The TEI0022 board provides an HDMI interface routed to the Intel Cyclone FPGA (U10). The HDMI interface is created by the HDMI transmitter ADV7511 provided by Analog Devices. The HDMI transmitter is incorporated in conjunction with the HDMI protection circuit TI TPD12S016 for more signal robustness.

HDMI connector J11Signal Schematic NameConnected toNotes
Pin 1, 3HDMI_TX2_P / HDMI_TX2_NHDMI transmitter, Pin 43, 42also connected to HDMI protection circuit
Pin 4, 6HDMI_TX1_P / HDMI_TX1_N

HDMI transmitter, Pin 40, 39

also connected to HDMI protection circuit

Pin 7, 9HDMI_TX0_P / HDMI_TX0_NHDMI transmitter, Pin 36, 35also connected to HDMI protection circuit
Pin 10, 12HDMI_TXC_P / HDMI_TXC_NHDMI transmitter, Pin 33, 32also connected to HDMI protection circuit
Pin 13CEC_BHDMI transmitter, Pin 48HDMI CEC, wired through HDMI protection circuit
Pin 15SCL_BHDMI transmitter, Pin 53HDMI I²C clock line, wired through HDMI protection circuit
Pin 16SDA_BHDMI transmitter, Pin 54HDMI I²C data line, wired through HDMI protection circuit
Pin 19HPD_BHDMI transmitter, Pin 30Hot Plug Detect, wired through HDMI protection circuit
Pin 185V_HDMIHDMI protection circuit, Pin 135V supply voltage, wired through HDMI protection circuit


FTDI (JTAG)

Please refer to the section "Micro USB Connector (JTAG)".

FTDI (UART)

Please refer to the section "Micro USB Connector (UART)".

DIP-Switches

There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

DIP-Switch S2

The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:

DIP-switch S2Position ONPosition OFFNotes
S4-1HPS_SW1 is lowHPS_SW1 is highUser switch
S4-2HPS_SW2 is lowHPS_SW2 is highUser switch
S4-3FPGA_SW1 is lowFPGA_SW1 is highUser switch
S4-4FPGA_SW2 is lowFPGA_SW2 is highUser switch


DIP-Switch S7

The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:

DIP-switch S7Position ONPosition OFFNotes
S7-1HPS_SPI_SS/BOOTSEL0 is lowHPS_SPI_SS/BOOTSEL0 is highBoot select (Firmware dependent)
S7-2QSPI_CS/BOOTSEL1 is lowQSPI_CS/BOOTSEL1 is highBoot select (Firmware dependent)
S7-3JTAGSEL0 is lowJTAGSEL0 is highJTAG select (Firmware dependent)
S7-4JTAGSEL1 is lowJTAGSEL1 is highJTAG select (Firmware dependent)


DIP-Switch S8

The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:

DIP-switch S8Position ONPosition OFFNotes
S8-1VID0_SW is lowVID0_SW is highFMC_VADJ selection (Firmware dependent)
S8-2VID1_SW is lowVID1_SW is highFMC_VADJ selection (Firmware dependent)
S8-3VID2_SW is lowVID2_SW is highFMC_VADJ selection (Firmware dependent)
S8-4JTAGEN is highJTAGEN is lowJTAG select


Buttons

There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.

ButtonPosition ONPosition OFFNotes
S1HPS_RST#_SW is lowHPS_RST#_SW is highReset (cold) the Intel Cyclone V HPS (Firmware dependent)
S3HPS_WARM_RST#_SW is lowHPS_WARM_RST#_SW is highReset (warm) the Intel Cyclone V HPS (Firmware dependent)
S4FPGA_RST#_SW is lowFPGA_RST#_SW is highReset the Intel Cyclone V FPGA (Firmware dependent)
S5USER_BTN_SW is lowUSER_BTN_SW is highUser button (Firmware dependent)


On-Board LEDs

The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.

DesignatorColorConnected toActive LevelNote
D11GreenIntel Cyclone V HPSHUser LED
D12GreenIntel Cyclone V HPSHUser LED
D13GreenIntel Cyclone V FPGAHUser LED
D14GreenIntel Cyclone V FPGAHUser LED
D8GreenIntel Cyclone V FPGA, Intel MAX 10LStatus: Configuration "Done"
D15GreenFT234XDLUART
D18GreenUART TXLUART
D19GreenUART RXLUART
D21Green+12.0VHStatus of +12.0V voltage rail
D1Green+12.0V_FMCHStatus of +12.0V_FMC voltage rail
D2Green+5.0VHStatus of +5.0V voltage rail
D3Green+3.3VHStatus of +3.3V voltage rail
D20Green+3.3V_MAX10HStatus of +3.3V_MAX10 voltage rail
D22Green+3.3V_FMCHStatus of +3.3V_FMC voltage rail
D4Green+2.5VHStatus of +2.5V voltage rail
D5GreenIntel MAX 10HStatus of +1.8V voltage rail
D7GreenIntel MAX 10HStatus of VCC voltage rail
D9GreenIntel MAX 10HStatus of FMC_VADJ voltage rail
D6GreenIntel MAX 10HStatus of VDD_DDR_FPGA voltage rail
D23GreenIntel MAX 10HStatus of VDD_DDR_HPS voltage rail
D17GreenIntel MAX 10HStatus of VTT_DDR_FPGA voltage rail
D10GreenIntel MAX 10HStatus of VTT_DDR_HPS voltage rail
D25RedIntel MAX 10HStatus


Temperature Sensor

The temperature sensor ADT7410 (U16) is implemented on the TEI0022 board.

Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA or the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Quad SPI Flash memory U6 is connected to the HPS bank 7B and U15 to FPGA bank 3A.

Signal NameQSPI Flash Memory U6 PinFPGA Pin
QSPI_CS/BOOTSEL1S#, Pin C2Bank 7B, Pin A18
QSPI_CLKC, Pin B2Bank 7B, Pin D19
QSPI_DATA0DQ0, Pin D3Bank 7B, Pin C20
QSPI_DATA1DQ1, Pin D2Bank 7B, Pin H18
QSPI_DATA2DQ2, Pin C4Bank 7B, Pin A19
QSPI_DATA3DQ3, Pin D4Bank 7B, Pin E19



Signal NameQSPI Flash Memory U15 PinFPGA Pin
nCSOS#, Pin C2Bank 3A, Pin AB8
AS_DCKC, Pin B2Bank 3A, Pin U7
AS_DATA0DQ0, Pin D3Bank 3A, Pin AE6
AS_DATA1DQ1, Pin D2Bank 3A, Pin AE5
AS_DATA2DQ2, Pin C4Bank 3A, Pin AE8
AS_DATA3DQ3, Pin D4Bank 3A, Pin AC7


EEPROM

The TEI0022 board contains two EEPROMs for configuration and general user purposes.

EEPROM ModelI2C AddressDesignatorMemory DensityPurposeNotes
24AA025E48T-I/OT0x50U382 KBitEthernet MAC--
93AA56BT-I/OT-U312 KBitJTAG Configuration--


Clock Sources

The board has following reference clocking sources provided by on-board oscillators:

Clock SourceFrequencySignal Schematic NameClock DestinationNotes
U48, SiT8208AI


25.0 MHz


CLK_25MHz_R

Si5338A PLL U3, Pin 3 (IN3)--
HPS_CLK1_25MHzHPS Bank 7A U10, Pin D25--
ETH_XTAL_INETH PHY U1, Pin 9--
U32, SiT8208AI12.0 MHzOSCIFT2232H U21, Pin 3--
U34, SiT8008BI24.0 MHzUSB_CLK24_HUBUSB Hub U33, Pin 33--
USB_CLK24_PHYUSB PHY U8, Pin 26--


Programmable Clock Generator

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U3) to generate various reference clocks for the module.  The I2C Address is 0x70.

Si5338A PinSignalConnected toDirectionDefault frequencyIO StandardNotes

IN1

SMA_CLK_INSMA J18, Pin 1Input----

Assembly option dependent

IN2SMA_CLK_INSMA J18, Pin 1Input----

Assembly option dependent

IN3

CLK_25MHz_R

U48, Pin 3Input25MHz--Reference input clock

IN4

--GNDInput----I2C slave device address LSB

IN5

--

Not ConnectedInput----Not used
IN6--GNDInput----Not used
SCLHPS_I2C_SCLCyclone V Bank 7A/Pin H23Input----

I²C interface

SDAHPS_I2C_SDACyclone V Bank 7A/Pin A25Input / Output----

I²C interface

CLK0A/B

SMA_CLK_OUT_p/n

SMA, J7/J10Output50MHzLVDS 3.3V

Assembly option dependent

CLK1A/B

CLK_B3B_p/nCyclone V FPGA Bank 3B/Pin AF14/AF15Output50MHzLVDS 1.8V--
CLK2ACLK_MAX10MAX10 Bank 2/Pin H6Output25MHzCMOS 3.3V

--

CLK2BHPS_CLK2Cyclone V HPS Bank 7A/Pin F25Output25MHzCMOS 3.3V--
CLK3A/B

CLK_B4A_p/n

Cyclone V FPGA Bank 4A/Pin AA16/AB17Output50MHzLVDS 1.8V

--


Power Monitoring

The TEI0022 uses a precision supply monitor (U54) for three voltages. Therefore, if one of the voltages browns out it should be realized and handled.

Power and Power-On Sequence



Enter the default value for power supply and startup of the module here.

  • Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Supply

The maximum power consumption of this board mainly depends on the design which is running on the FPGA. Intel provides power estimator excel sheets to calculate power consumption.

Power Consumption

Power Input PinTypical Current
+12.0V_INTBD*


* TBD - To Be Determined

Power Distribution Dependencies

All on-board voltages of the TEI0022 are generated out of the extern applied 12 V power supply.

There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:





Power-On Sequence

The following figures delivers the power-on sequence information. The figure Power Sequency shows the connections between the power devices and its management. The figure Suggested Power Sequency shows the recommended firmware power-on sequence. For more information about firmware depended power-on sequencing see TEI0022 Intel MAX 10 → Power mangement.








Voltage Monitor Circuit

The voltages +3.3V, +5.0V, and VCC are monitored by the voltage monitor circuit LTC2911 (U54), which generates a reset signal at power-on. A manual reset is also possible as described in the reset table.




Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 3A+3.3V+3.3 V--
Bank 3B

VDD_DDR_FPGA

+1.5 V--
Bank 4A

VDD_DDR_FPGA

+1.5 V--
Bank 5A+3.3V+3.3 V--
Bank 5B+3.3V+3.3 V--
Bank 6A

VDD_DDR_HPS

+1.5 V--
Bank 6B

VDD_DDR_HPS

+1.5 V--
Bank 7A+3.3V+3.3 V--
Bank 7B+3.3V+3.3 V--
Bank 7C+3.3V+3.3 V--
Bank 7D+3.3V+3.3 V--
Bank 8AFMC_VADJ

+3.3 V, +2.5 V, +1.8 V, +1.25 V, +1.2 V

Adjustable voltage (+0.8 V is not usable at the Intel Cyclone V)
Bank 9A+3.3V+3.3 V--



Technical Specifications



List of all Powerrails which are accessible by the customer

  • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
+12.0V_INInput Voltage-2525V


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
+12.0V_IN10.513VInput power protection U42


Physical Dimensions

  • Module size: 160 mm × 130 mm.  Please download the assembly diagram for exact numbers.

PCB thickness: 1.9 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 



Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TEI0022 overview page
English pageGerman page


Revision History


Hardware Revision History

Set correct links to download  Carrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD
  • Example: 

    DateRevisionChangesDocumentation Link
    2020-11-25REV02
    • Resistors R14 and R15 was replaced by 953R (was 5K1)
    • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
    REV02



DateRevisionChangesDocumentation Link
-03Refer to the "Revision_Changes" schematic page
-02Refer to the "Revision_Changes" schematic page
-01First Production Release


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • add default frequency and IO Standard to 'Programmable Clock Generator'
  • Style update

2022-06-15

v.55

Thomas Dück

  • typo correction
2020-11-03v.52ED
  • Update TRM to REV03
2020-06-03v.48TD
  • Chapter 'Power-On Sequence' updated
2020-02-26v.47ED
  • Update TRM to REV02

--

all

  • Initial Document


Disclaimer




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