Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TE0022-01 board is an industrial-grade SoC module based on Intel Cyclone V FPGA, a Ethernet PHY, one GByte DDR3 SDRAM per HPS and FPGA, two 32 MByte Quad SPI Flash memory for configuration and operation and powerful switching-mode power supplies for all on-board voltages.
Refer to http://trenz.org/tei0022-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modues: - SoC/FPGA
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)
- RAM/Storage
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
- On Board
- 4 x SMA Connector
- Temperature Sensor
- Intel MAX10
- Interface
- LPC FMC Connector
- 4 x PMOD Connector
- JTAG via micro USB B Connector
- UART via
- micro USB B Connector
- 4 x USB 2.0
- Ethernet via RJ45 Connector
- SD Card
- HDMI
- Power
- 12 V Input supply voltage
- Dimension
Block Diagram
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Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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HPS SPI Flash | Not programmed | HPS Configuration | FPGA SPI Flash | Not programmed | FPGA Configuration | MAC EEPROM | Not Programmed | Ethernet MAC | System Controller | Programmed | Board Management | FTDI EEPROM | Programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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BOOTSEL[1..0] Signal State | Boot Mode |
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00 | FPGA | 01 | SD | 11 | SPI |
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Reset | Button | Note |
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HPS cold reset | S1 |
| HPS warm reset | S3 |
| FPGA reset | S4 |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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LPC FMC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
FMC Signal | Intel Cyclone V Direction | I/O Signal Count | Voltage Level | Notes |
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LA0...1 | RX and TX | 4 SE, 2 Diff | FMC_VADJ | Connected to RX and TX pins at the Intel Cyclone V | LA2...15 | RX | 28 SE, 14 Diff | FMC_VADJ |
| LA16 | TX | 2 SE, 1 Diff | FMC_VADJ |
| LA17...18 | RX | 4 SE, 2 Diff | FMC_VADJ |
| LA19...33 | TX | 28 SE, 14 Diff | FMC_VADJ |
| CLK0...1 | RX | 4 SE, 2 Diff | FMC_VADJ |
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JTAG Interface
According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 |
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X | X | ON | Intel MAX10 | ON | ON | OFF | Intel Cyclone V HPS | ON | OFF | OFF | Intel Cyclone V FPGA | OFF | ON | OFF | FMC |
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MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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MIO Pin | Connected to | B2B | Notes |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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Temperature Sensor | U16 |
| DDR3 SDRAM | U26...29 |
| Ethernet | U1 |
| SPI | U6, U15 |
| EEPROM | U38 |
| Intel Cyclone V | U10 |
| SD Card | J3 |
| Switch | S2 |
| JTAG | U21 |
| UART | U30 |
| HDMI | U23 |
| Intel MAX10 | U41 |
| PMOD | P1...4 |
| Power Monitoring | U54 |
| USB | U8 |
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Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
MIO Pin | Schematic | U?? Pin | Notes |
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RTC
MIO Pin | Schematic | U? Pin | Notes |
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EEPROM
MIO Pin | Schematic | U?? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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D11 | Green | Intel Cyclone V HPS | L | User LED | D12 | Green | Intel Cyclone V HPS | L | User LED | D13 | Green | Intel Cyclone V FPGA | L | User LED | D14 | Green | Intel Cyclone V FPGA | L | User LED | D8 | Green | Intel Cyclone V FPGA | L | Status: Configuration "Done" | D15 | Green | FT234XD | L | UART | D18 | Green | UART TX | H | UART | D19 | Green | UART RX | H | UART | D21 | Green | +12.0V | H | Status of +12.0V voltage rail | D1 | Green | +12.0V_FMC | H | Status of +12.0V_FMC voltage rail | D2 | Green | +5.0V | H | Status of +5.0V voltage rail | D3 | Green | +3.3V | H | Status of +3.3V voltage rail | D20 | Green | +3.3V_MAX10 | H | Status of +3.3V_MAX10 voltage rail | D22 | Green | +3.3V_FMC | H | Status of +3.3V_FMC voltage rail | D4 | Green | +2.5V | H | Status of +2.5V voltage rail | D5 | Green | +1.8V | H | Status of +1.8V voltage rail | D7 | Green | VCC | H | Status of VCC voltage rail | D9 | Green | FMC_VADJ | H | Status of FMC_VADJ voltage rail | D6 | Green | VDD_DDR_FPGA | H | Status of VDD_DDR_FPGA voltage rail | D23 | Green | VDD_DDR_HPS | H | Status of VDD_DDR_HPS voltage rail | D17 | Green | VTT_DDR_FPGA | H | Status of VTT_DDR_FPGA voltage rail | D10 | Green | VTT_DDR_HPS | H | Status of VTT_DDR_HPS voltage rail |
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DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA and HPS for storing user application code and data.
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 V
- Speed: ???
- Temperature: TC = -40 °C up to 95 °C
Ethernet
Bank | Signal Name | ETH | Signal Description |
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7B | ETH_TXCK |
| RGMII Transmit Reference Clock | 7B | ETH_TXD0 |
| RGMII Transmit Data 0 | 7B | ETH_TXD1 |
| RGMII Transmit Data 1 | 7B | ETH_TXD2 |
| RGMII Transmit Data 2 | 7B | ETH_TXD3 |
| RGMII Transmit Data 3 | 7B | ETH_TXCTL |
| RGMII Transmit Control | 7B | ETH_RXCK |
| RGMII Receive Reference Clock | 7B | ETH_RXD0 |
| RGMII Receive Data 0 | 7B | ETH_RXD1 |
| RGMII Receive Data 2 | 7B | ETH_RXD2 |
| RGMII Receive Data 3 | 7B | ETH_RXD3 |
| RGMII Receive Data 4 | 7B | ETH_RXCTL |
| RGMII Receive Control | 7C | ETH_RST |
| Reset | 7B | ETH_MDC |
| Management Data Clock | 7B | ETH_MDIO |
| Management Data I/O | 7B | PHY_INT |
| Interrupt |
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Clock Sources
Designator | Description | Frequency | Note |
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U2 | Ethernet | 25 MHz |
| U37 | FPGA | 50 MHz | Bank 5B and MAX10 | U35 | FPGA | 50 MHz | Bank 4A and 3B |
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| U44 | HPS | 24 MHz | CLK1, CLK2 | U32 | FTDI | 12 MHz |
| U3 | HDMI | 12 MHz |
| U34 | USB | 24 MHz |
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| HPS | 25 MHz | CLK1 HPS SOCKIT |
| HPS | 25 MHz | CLK2 HPS SOCKIT |
| FPGA | 50 MHz | Bank 3B SOCKIT |
| FPGA | 50 MHz | Bank 4A SOCKIT |
| FPGA | 50 MHz | Bank 5B SOCKIT |
| FPGA | 50 MHz | Bank 8A SOCKIT |
| FPGA | 50 MHz | Pin P8/9 SOCKIT |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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Power-On Sequence
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Voltage Monitor Circuit
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Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
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Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Revision | Contributor | Description |
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Disclaimer