Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
----------------------------------------------------------------------- |
Note for Download Link of the Scroll ignore macro: |
Table of Contents |
Overview
The Trenz Electronic TE0022-01 board is an industrial-grade SoC module based on Intel Cyclone V FPGA, an ethernet PHY, one GByte DDR3 SDRAM and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.
Refer to http://trenz.org/tei0022-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modues: - SoC/FPGA
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
|
- SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)
- RAM/Storage
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
- On Board
- 4 x SMA Connector
- Temperature Sensor
- Intel MAX10
- Interface
- LPC FMC Connector
- 4 x PMOD Connector
- JTAG via micro USB B Connector
- UART via
- micro USB B Connector
- 4 x USB 2.0
- Ethernet via RJ45 Connector
- SD Card
- HDMI
- Power
- 12 V Input supply voltage
- Dimension
Block Diagram
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
- ...
- ...
- ...
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
---|
HPS SPI Flash | Not programmed | HPS Configuration | FPGA SPI Flash | Not programmed | FPGA Configuration | MAC EEPROM | Not Programmed | Ethernet MAC | System Controller | Programmed | Board Management | FTDI EEPROM | Programmed |
|
|
Configuration Signals
- Overview of Boot Mode, Reset, Enables.
|
BOOTSEL[1..0] Signal State | Boot Mode |
---|
00 | FPGA | 01 | SD | 11 | SPI |
|
Reset | Button | Note |
---|
HPS cold reset | S1 |
| HPS warm reset | S3 |
| FPGA reset | S4 |
|
|
Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
|
LPC FMC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
FMC Signal | Intel Cyclone V Direction | I/O Signal Count | Voltage Level | Notes |
---|
LA0...1 | RX and TX | 4 SE, 2 Diff | FMC_VADJ | Connected to RX and TX pins at the Intel Cyclone V | LA2...15 | RX | 28 SE, 14 Diff | FMC_VADJ |
| LA16 | TX | 2 SE, 1 Diff | FMC_VADJ |
| LA17...18 | RX | 4 SE, 2 Diff | FMC_VADJ |
| LA19...33 | TX | 28 SE, 14 Diff | FMC_VADJ |
| CLK0...1 | RX | 4 SE, 2 Diff | FMC_VADJ |
|
|
JTAG Interface
According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 |
---|
X | X | ON | Intel MAX10 | ON | ON | OFF | Intel Cyclone V HPS | ON | OFF | OFF | Intel Cyclone V FPGA | OFF | ON | OFF | FMC |
|
On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
---|
Temperature Sensor | U16 |
| QSPI | U6, U15 |
| EEPROM | U38 |
|
|
|
|
|
|
| Intel Cyclone V | U10 |
| SD Card | J3 |
| Switch | S2 |
| JTAG | U21 |
| UART | U30 |
| HDMI | U23 |
| Intel MAX10 | U41 |
| PMOD | P1...4 |
| Power Monitoring | U54 |
| USB | U8 |
| Ethernet | U1 |
| DDR3 SDRAM | U26...29 |
|
|
Temperatur Sensor
The temperature sensor ADT7410 is implemented on the TEI0022 board.
Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
There are two QSPI flash memory components implemented. One of them is used for the HPS (U6) and the other for the FPGA (U15). The flash memory is connected to its specific interface.
EEPROM
On the board are two EEPROMs used. One is used for the JTAG configuration (U31). The other is used for the ethernet MAC (U38). The last one is connected via I2C connection as specified in the table.
Pin | I2C Address | Designator | Notes |
---|
HPS: A25, H23 | 0x50 | U38 | Ethernet MAC |
|
LEDs
Designator | Color | Connected to | Active Level | Note |
---|
D11 | Green | Intel Cyclone V HPS | L | User LED | D12 | Green | Intel Cyclone V HPS | L | User LED | D13 | Green | Intel Cyclone V FPGA | L | User LED | D14 | Green | Intel Cyclone V FPGA | L | User LED | D8 | Green | Intel Cyclone V FPGA | L | Status: Configuration "Done" | D15 | Green | FT234XD | L | UART | D18 | Green | UART TX | H | UART | D19 | Green | UART RX | H | UART | D21 | Green | +12.0V | H | Status of +12.0V voltage rail | D1 | Green | +12.0V_FMC | H | Status of +12.0V_FMC voltage rail | D2 | Green | +5.0V | H | Status of +5.0V voltage rail | D3 | Green | +3.3V | H | Status of +3.3V voltage rail | D20 | Green | +3.3V_MAX10 | H | Status of +3.3V_MAX10 voltage rail | D22 | Green | +3.3V_FMC | H | Status of +3.3V_FMC voltage rail | D4 | Green | +2.5V | H | Status of +2.5V voltage rail | D5 | Green | +1.8V | H | Status of +1.8V voltage rail | D7 | Green | VCC | H | Status of VCC voltage rail | D9 | Green | FMC_VADJ | H | Status of FMC_VADJ voltage rail | D6 | Green | VDD_DDR_FPGA | H | Status of VDD_DDR_FPGA voltage rail | D23 | Green | VDD_DDR_HPS | H | Status of VDD_DDR_HPS voltage rail | D17 | Green | VTT_DDR_FPGA | H | Status of VTT_DDR_FPGA voltage rail | D10 | Green | VTT_DDR_HPS | H | Status of VTT_DDR_HPS voltage rail |
|
DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA and HPS for storing user application code and data.
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 V
- Speed: ???
- Temperature: TC = -40 °C up to 95 °C
Ethernet
Bank | Signal Name | ETH | Signal Description |
---|
7B | ETH_TXCK |
| RGMII Transmit Reference Clock | 7B | ETH_TXD0 |
| RGMII Transmit Data 0 | 7B | ETH_TXD1 |
| RGMII Transmit Data 1 | 7B | ETH_TXD2 |
| RGMII Transmit Data 2 | 7B | ETH_TXD3 |
| RGMII Transmit Data 3 | 7B | ETH_TXCTL |
| RGMII Transmit Control | 7B | ETH_RXCK |
| RGMII Receive Reference Clock | 7B | ETH_RXD0 |
| RGMII Receive Data 0 | 7B | ETH_RXD1 |
| RGMII Receive Data 2 | 7B | ETH_RXD2 |
| RGMII Receive Data 3 | 7B | ETH_RXD3 |
| RGMII Receive Data 4 | 7B | ETH_RXCTL |
| RGMII Receive Control | 7C | ETH_RST |
| Reset | 7B | ETH_MDC |
| Management Data Clock | 7B | ETH_MDIO |
| Management Data I/O | 7B | PHY_INT |
| Interrupt |
|
Clock Sources
Designator | Description | Frequency | Note |
---|
U2 | Ethernet | 25 MHz |
| U37 | FPGA | 50 MHz | Bank 5B and MAX10 | U35 | FPGA | 50 MHz | Bank 4A and 3B |
|
|
|
| U44 | HPS | 25 MHz | CLK1, CLK2 | U32 | FTDI | 12 MHz |
| U3 | HDMI | 12 MHz |
| U34 | USB | 24 MHz |
|
|
|
|
|
|
|
|
|
| HPS | 25 MHz | CLK1 HPS SOCKIT |
| HPS | 25 MHz | CLK2 HPS SOCKIT |
| FPGA | 50 MHz | Bank 3B SOCKIT |
| FPGA | 50 MHz | Bank 4A SOCKIT |
| FPGA | 50 MHz | Bank 5B SOCKIT |
| FPGA | 50 MHz | Bank 8A SOCKIT |
| FPGA | 50 MHz | Pin P8/9 SOCKIT |
|
|
|
|
|
Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
---|
VIN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Power-On Sequence
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Voltage Monitor Circuit
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
---|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
|
? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
---|
|
|
|
| V |
|
|
|
| V |
|
|
|
| V |
|
|
|
| V |
|
|
|
| V |
|
|
|
| V |
|
|
|
| V |
|
|
|
| V |
|
|
|
|
|
|
|
|
|
|
|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|
|
|
| V | See ???? datasheets. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| °C | See Xilinx ???? datasheet. |
|
|
| °C | See Xilinx ???? datasheet. |
|
Physical Dimensions
PCB thickness: ?? mm.
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
---|
- |
|
|
|
|
|
|
|
|
|
|
|
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Date | Revision | Contributor | Description |
---|
| | | | -- | all | | |
|
Disclaimer