Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>


Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TE0022-01 board is an industrial-grade SoC module based on Intel Cyclone V FPGA, an ethernet PHY, one GByte DDR3 SDRAM and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.

Refer to http://trenz.org/tei0022-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modues:

  • SoC/FPGA
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension



Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .




Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .




Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


  1. ...
  2. ...
  3. ...

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

HPS SPI Flash

Not programmed

HPS Configuration

FPGA SPI FlashNot programmedFPGA Configuration
MAC EEPROMNot Programmed

Ethernet MAC

System ControllerProgrammedBoard Management
FTDI EEPROMProgrammed


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.


BOOTSEL[1..0] Signal State

Boot Mode

00

FPGA

01SD
11SPI




Reset

ButtonNote

HPS cold reset

S1
HPS warm resetS3
FPGA resetS4


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

FMC LPC Connector

The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.

The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

FMC SignalIntel Cyclone V DirectionI/O Signal Count (Single Ended/Differential)Voltage LevelNotes
LA0...1RX and TX4 / 2FMC_VADJConnected to RX and TX pins at the Intel Cyclone V
LA2...15, LA17...18RX32 / 16FMC_VADJ
LA16, LA19...33TX32 / 16FMC_VADJ
CLK0...1RX4 / 2FMC_VADJ


The FMC connector provides further interfaces like JTAG and I²C interfaces:

InterfaceI/O Signal CountPin schematic Names / FMC PinsConnected toNotes
JTAG5

FMC_TCK, Pin J4-D29

FMC_TMS, Pin J4-D33

FMC_TDI, Pin J4-D30

FMC_TDO, Pin J4- D31

FMC_TRST#, Pin J4- D34

Intel MAX10 U41, Bank 3VCCIO: +3.3V
I2C2

FMC_SCL, Pin J4-C30

FMC_SDA, Pin J4-C31

Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7AI2C-lines pulled-up to +3.3V










Control Lines4FMC_PRSNT_M2C#, Pin J4-H2




FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)


Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

VCCIO Schematic NameFMC Connector J4 PinsNotes
+12.0V_FMCC35/C37extern 12V power supply
+3.3V_FMCD36/D38/D40/C393.3V peripheral supply voltage
+3.3VD323.3V peripheral supply voltage
FMC_VADJH40/G39adjustable FMC VCCIO voltage, supplied by DC-DC converter U43


JTAG Interface

According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.

JTAGSEL1

JTAGSEL0

JTAGSEL1

JTAGSEL0
XXONIntel MAX10
ONONOFFIntel Cyclone V HPS
ONOFFOFFIntel Cyclone V FPGA
OFFONOFFFMC


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
Temperature SensorU16
QSPIU6, U15
EEPROMU38
LEDD1...15, D17...23
DDR3 SDRAMU26...29
EthernetU1
Clock SourcesU...



SwitchS2
JTAGU21
UARTU30
HDMIU23
Intel MAX10U41
PMODP1...4
Power MonitoringU54
USBU8
SD CardJ3
Intel Cyclone VU10


Temperatur Sensor

The temperature sensor ADT7410 is implemented on the TEI0022 board.

Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

There are two QSPI flash memory components implemented. One of them is used for the HPS (U6) and the other for the FPGA (U15). The flash memory is connected to its specific interface.

I2C

The TEI0022 provides two independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The other bus is used to handle the on-board I2C devices.

BusI2C DeviceDesignatorI2C AddressSchematic Names of I2C Bus LinesNotes
HPS I2CTemperature Sensor0x4AU16HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CEEPROM0x50U38HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CHDMI0x72U23HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS FMC I2CFMC0x50J4FMC_SCL / FMC_SDA3.3 V reference voltage


System Controller Intel MAX10

The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.

EEPROM

The TEI0022 board contains two EEPROMs for configuration and general user purposes.

EEPROM ModelI2C AddressDesignatorMemory DensityPurposeNotes
24AA025E48T-I/OT0x50U382 KBitEthernet MAC
93AA56BT-I/OT-U312 KBitJTAG Configuration


High-speed USB ULPI PHY

USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).

PHY PinConnected toNotes
ULPIIntel Cyclone V HPS (U10)
REFCLK24 MHz from on board oscillator (U34)
REFSEL[0..2]High (3.3 V)
RESETBIntel Cyclone V HPS (U10)
DP, DM4-port USB 2.0 Hub (U33)
CPENNot Connected.
VBUSPull-up to 5 V.
IDNot Connected.


4-Port USB 2.0 Hub

On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available. The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.

Buttons

There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.

ButtonPosition ONPosition OFFNotes
S1HPS_RST#_SW is highHPS_RST#_SW is lowReset (cold) the Intel Cyclone V HPS
S3HPS_WARM_RST#_SW is highHPS_WARM_RST#_SW is lowReset (warm) the Intel Cyclone V HPS
S4FPGA_RST#_SW is highFPGA_RST#_SW is lowReset the Intel Cyclone V FPGA
S5USER_BTN_SW is highUSER_BTN_SW is lowUser button


DIP-Switches

There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

DIP-switch S2

The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:

DIP-switch S2Position ONPosition OFFNotes
S4-1HPS_SW1 is lowHPS_SW1 is highUser switch
S4-2HPS_SW2 is lowHPS_SW2 is highUser switch
S4-3FPGA_SW1 is lowFPGA_SW1 is highUser switch
S4-4FPGA_SW2 is lowFPGA_SW2 is highUser switch


DIP-switch S7

The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:

DIP-switch S7Position ONPosition OFFNotes
S7-1HPS_SPI_SS/BOOTSEL0 is lowHPS_SPI_SS/BOOTSEL0 is highBoot select
S7-2QSPI_CS/BOOTSEL1 is lowQSPI_CS/BOOTSEL1 is highBoot select
S7-3JTAGSEL0 is lowJTAGSEL0 is highJTAG select
S7-4JTAGSEL1 is lowJTAGSEL1 is highJTAG select


DIP-switch S8

The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:

DIP-switch S8Position ONPosition OFFNotes
S8-1JTAGEN is highJTAGEN is lowJTAG select
S8-2VID0_SW is lowVID0_SW is highFMC_VADJ selection
S8-3VID1_SW is lowVID1_SW is highFMC_VADJ selection
S8-4VID2_SW is lowVID2_SW is highFMC_VADJ selection


On-board LEDs

The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.

DesignatorColorConnected toActive LevelNote
D11GreenIntel Cyclone V HPSLUser LED
D12GreenIntel Cyclone V HPSLUser LED
D13GreenIntel Cyclone V FPGALUser LED
D14GreenIntel Cyclone V FPGALUser LED
D8GreenIntel Cyclone V FPGALStatus: Configuration "Done"
D15GreenFT234XDLUART
D18GreenUART TXHUART
D19GreenUART RXHUART
D21Green+12.0VHStatus of +12.0V voltage rail
D1Green+12.0V_FMCHStatus of +12.0V_FMC voltage rail
D2Green+5.0VHStatus of +5.0V voltage rail
D3Green+3.3VHStatus of +3.3V voltage rail
D20Green+3.3V_MAX10HStatus of +3.3V_MAX10 voltage rail
D22Green+3.3V_FMCHStatus of +3.3V_FMC voltage rail
D4Green+2.5VHStatus of +2.5V voltage rail
D5Green+1.8VHStatus of +1.8V voltage rail
D7GreenVCCHStatus of VCC voltage rail
D9GreenFMC_VADJHStatus of FMC_VADJ voltage rail
D6GreenVDD_DDR_FPGAHStatus of VDD_DDR_FPGA voltage rail
D23GreenVDD_DDR_HPSHStatus of VDD_DDR_HPS voltage rail
D17GreenVTT_DDR_FPGAHStatus of VTT_DDR_FPGA voltage rail
D10GreenVTT_DDR_HPSHStatus of VTT_DDR_HPS voltage rail


DDR3 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA and HPS for storing user application code and data.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U2).

BankSignal NameETHSignal Description
7BETH_TXCK
RGMII Transmit Reference Clock
7BETH_TXD0
RGMII Transmit Data 0
7BETH_TXD1
RGMII Transmit Data 1
7BETH_TXD2
RGMII Transmit Data 2
7BETH_TXD3
RGMII Transmit Data 3
7B

ETH_TXCTL


RGMII Transmit Control
7BETH_RXCK
RGMII Receive Reference Clock
7BETH_RXD0
RGMII Receive Data 0
7BETH_RXD1
RGMII Receive Data 2
7BETH_RXD2
RGMII Receive Data 3
7BETH_RXD3
RGMII Receive Data 4
7B

ETH_RXCTL


RGMII Receive Control
7CETH_RST
Reset
7BETH_MDC
Management Data Clock
7BETH_MDIO
Management Data I/O
7BPHY_INT
Interrupt



Oscillators

DesignatorDescriptionFrequencyNote
U2Ethernet25 MHz
U37FPGA50 MHzBank 5B and MAX10
U35FPGA50 MHzBank 4A and 3B




U44HPS25 MHzCLK1, CLK2
U32FTDI12 MHz
U3HDMI12 MHz
U34USB24 MHz











HPS25 MHzCLK1 HPS SOCKIT

HPS25 MHzCLK2 HPS SOCKIT

FPGA50 MHzBank 3B SOCKIT

FPGA50 MHzBank 4A SOCKIT

FPGA50 MHzBank 5B SOCKIT

FPGA50 MHzBank 8A SOCKIT

FPGA50 MHzPin P8/9 SOCKIT





Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Power-On Sequence


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Voltage Monitor Circuit


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Power Rails


Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit




V




V




V




V




V




V




V




V











Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.


Physical Dimensions

PCB thickness: ?? mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .




Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
-











Hardware revision number can be found on the PCB board together with the module model number separated by the dash.


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • change list

--

all

  • --


Disclaimer