Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TE0022-01 board is an industrial-grade SoC module based on Intel Cyclone V FPGA, an ethernet PHY, one GByte DDR3 SDRAM and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.
Refer to http://trenz.org/tei0022-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modues: - SoC/FPGA
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)
- RAM/Storage
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
- On Board
- 4 x SMA Connector
- Temperature Sensor
- Intel MAX10
- Interface
- LPC FMC Connector
- 4 x PMOD Connector
- JTAG via micro USB B Connector
- UART via
- micro USB B Connector
- 4 x USB 2.0
- Ethernet via RJ45 Connector
- SD Card
- HDMI
- Power
- 12 V Input supply voltage
- Dimension
Block Diagram
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Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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HPS SPI Flash | Not programmed | HPS Configuration | FPGA SPI Flash | Not programmed | FPGA Configuration | MAC EEPROM | Not Programmed | Ethernet MAC | System Controller | Programmed | Board Management | FTDI EEPROM | Programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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BOOTSEL[1..0] Signal State | Boot Mode |
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00 | FPGA | 01 | SD | 11 | SPI |
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Reset | Button | Note |
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HPS cold reset | S1 |
| HPS warm reset | S3 |
| FPGA reset | S4 |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
FMC Signal | Intel Cyclone V Direction | I/O Signal Count (Single Ended/Differential) | Voltage Level | Notes |
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LA0...1 | RX and TX | 4 / 2 | FMC_VADJ | Connected to RX and TX pins at the Intel Cyclone V | LA2...15, LA17...18 | RX | 32 / 16 | FMC_VADJ |
| LA16, LA19...33 | TX | 32 / 16 | FMC_VADJ |
| CLK0...1 | RX | 4 / 2 | FMC_VADJ |
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The FMC connector provides further interfaces like JTAG and I²C interfaces:
Interface | I/O Signal Count | Pin schematic Names / FMC Pins | Connected to | Notes |
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JTAG | 5 | FMC_TCK, Pin J4-D29 FMC_TMS, Pin J4-D33 FMC_TDI, Pin J4-D30 FMC_TDO, Pin J4- D31 FMC_TRST#, Pin J4- D34 | Intel MAX10 U41, Bank 3 | VCCIO: +3.3V | I2C | 2 | FMC_SCL, Pin J4-C30 FMC_SDA, Pin J4-C31 | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7A | I2C-lines pulled-up to +3.3V |
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| Control Lines | 4 | FMC_PRSNT_M2C#, Pin J4-H2 |
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| FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V) |
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Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:
VCCIO Schematic Name | FMC Connector J4 Pins | Notes |
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+12.0V_FMC | C35/C37 | extern 12V power supply | +3.3V_FMC | D36/D38/D40/C39 | 3.3V peripheral supply voltage | +3.3V | D32 | 3.3V peripheral supply voltage | FMC_VADJ | H40/G39 | adjustable FMC VCCIO voltage, supplied by DC-DC converter U43 |
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JTAG Interface
According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 |
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X | X | ON | Intel MAX10 | ON | ON | OFF | Intel Cyclone V HPS | ON | OFF | OFF | Intel Cyclone V FPGA | OFF | ON | OFF | FMC |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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Temperature Sensor | U16 |
| QSPI | U6, U15 |
| EEPROM | U38 |
| LED | D1...15, D17...23 |
| DDR3 SDRAM | U26...29 |
| Ethernet | U1 |
| Clock Sources | U... |
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| Switch | S2 |
| JTAG | U21 |
| UART | U30 |
| HDMI | U23 |
| Intel MAX10 | U41 |
| PMOD | P1...4 |
| Power Monitoring | U54 |
| USB | U8 |
| SD Card | J3 |
| Intel Cyclone V | U10 |
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Temperatur Sensor
The temperature sensor ADT7410 is implemented on the TEI0022 board.
Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
There are two QSPI flash memory components implemented. One of them is used for the HPS (U6) and the other for the FPGA (U15). The flash memory is connected to its specific interface.
I2C
The TEI0022 provides two independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The other bus is used to handle the on-board I2C devices.
Bus | I2C Device | Designator | I2C Address | Schematic Names of I2C Bus Lines | Notes |
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HPS I2C | Temperature Sensor | 0x4A | U16 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | HPS I2C | EEPROM | 0x50 | U38 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | HPS I2C | HDMI | 0x72 | U23 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | HPS FMC I2C | FMC | 0x50 | J4 | FMC_SCL / FMC_SDA | 3.3 V reference voltage |
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System Controller Intel MAX10
The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.
EEPROM
The TEI0022 board contains two EEPROMs for configuration and general user purposes.
EEPROM Model | I2C Address | Designator | Memory Density | Purpose | Notes |
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24AA025E48T-I/OT | 0x50 | U38 | 2 KBit | Ethernet MAC |
| 93AA56BT-I/OT | - | U31 | 2 KBit | JTAG Configuration |
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High-speed USB ULPI PHY
USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).
PHY Pin | Connected to | Notes |
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ULPI | Intel Cyclone V HPS (U10) |
| REFCLK | 24 MHz from on board oscillator (U34) |
| REFSEL[0..2] | High (3.3 V) |
| RESETB | Intel Cyclone V HPS (U10) |
| DP, DM | 4-port USB 2.0 Hub (U33) |
| CPEN | Not Connected. |
| VBUS | Pull-up to 5 V. |
| ID | Not Connected. |
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4-Port USB 2.0 Hub
On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available. The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.
Buttons
There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.
Button | Position ON | Position OFF | Notes |
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S1 | HPS_RST#_SW is high | HPS_RST#_SW is low | Reset (cold) the Intel Cyclone V HPS | S3 | HPS_WARM_RST#_SW is high | HPS_WARM_RST#_SW is low | Reset (warm) the Intel Cyclone V HPS | S4 | FPGA_RST#_SW is high | FPGA_RST#_SW is low | Reset the Intel Cyclone V FPGA | S5 | USER_BTN_SW is high | USER_BTN_SW is low | User button |
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DIP-Switches
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
DIP-switch S2
The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:
DIP-switch S2 | Position ON | Position OFF | Notes |
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S4-1 | HPS_SW1 is low | HPS_SW1 is high | User switch | S4-2 | HPS_SW2 is low | HPS_SW2 is high | User switch | S4-3 | FPGA_SW1 is low | FPGA_SW1 is high | User switch | S4-4 | FPGA_SW2 is low | FPGA_SW2 is high | User switch |
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DIP-switch S7
The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:
DIP-switch S7 | Position ON | Position OFF | Notes |
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S7-1 | HPS_SPI_SS/BOOTSEL0 is low | HPS_SPI_SS/BOOTSEL0 is high | Boot select | S7-2 | QSPI_CS/BOOTSEL1 is low | QSPI_CS/BOOTSEL1 is high | Boot select | S7-3 | JTAGSEL0 is low | JTAGSEL0 is high | JTAG select | S7-4 | JTAGSEL1 is low | JTAGSEL1 is high | JTAG select |
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DIP-switch S8
The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:
DIP-switch S8 | Position ON | Position OFF | Notes |
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S8-1 | JTAGEN is high | JTAGEN is low | JTAG select | S8-2 | VID0_SW is low | VID0_SW is high | FMC_VADJ selection | S8-3 | VID1_SW is low | VID1_SW is high | FMC_VADJ selection | S8-4 | VID2_SW is low | VID2_SW is high | FMC_VADJ selection |
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On-board LEDs
The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.
Designator | Color | Connected to | Active Level | Note |
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D11 | Green | Intel Cyclone V HPS | L | User LED | D12 | Green | Intel Cyclone V HPS | L | User LED | D13 | Green | Intel Cyclone V FPGA | L | User LED | D14 | Green | Intel Cyclone V FPGA | L | User LED | D8 | Green | Intel Cyclone V FPGA | L | Status: Configuration "Done" | D15 | Green | FT234XD | L | UART | D18 | Green | UART TX | H | UART | D19 | Green | UART RX | H | UART | D21 | Green | +12.0V | H | Status of +12.0V voltage rail | D1 | Green | +12.0V_FMC | H | Status of +12.0V_FMC voltage rail | D2 | Green | +5.0V | H | Status of +5.0V voltage rail | D3 | Green | +3.3V | H | Status of +3.3V voltage rail | D20 | Green | +3.3V_MAX10 | H | Status of +3.3V_MAX10 voltage rail | D22 | Green | +3.3V_FMC | H | Status of +3.3V_FMC voltage rail | D4 | Green | +2.5V | H | Status of +2.5V voltage rail | D5 | Green | +1.8V | H | Status of +1.8V voltage rail | D7 | Green | VCC | H | Status of VCC voltage rail | D9 | Green | FMC_VADJ | H | Status of FMC_VADJ voltage rail | D6 | Green | VDD_DDR_FPGA | H | Status of VDD_DDR_FPGA voltage rail | D23 | Green | VDD_DDR_HPS | H | Status of VDD_DDR_HPS voltage rail | D17 | Green | VTT_DDR_FPGA | H | Status of VTT_DDR_FPGA voltage rail | D10 | Green | VTT_DDR_HPS | H | Status of VTT_DDR_HPS voltage rail |
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DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA and HPS for storing user application code and data.
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 V
- Speed: ???
- Temperature: TC = -40 °C up to 95 °C
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U2).
Bank | Signal Name | ETH | Signal Description |
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7B | ETH_TXCK |
| RGMII Transmit Reference Clock | 7B | ETH_TXD0 |
| RGMII Transmit Data 0 | 7B | ETH_TXD1 |
| RGMII Transmit Data 1 | 7B | ETH_TXD2 |
| RGMII Transmit Data 2 | 7B | ETH_TXD3 |
| RGMII Transmit Data 3 | 7B | ETH_TXCTL |
| RGMII Transmit Control | 7B | ETH_RXCK |
| RGMII Receive Reference Clock | 7B | ETH_RXD0 |
| RGMII Receive Data 0 | 7B | ETH_RXD1 |
| RGMII Receive Data 2 | 7B | ETH_RXD2 |
| RGMII Receive Data 3 | 7B | ETH_RXD3 |
| RGMII Receive Data 4 | 7B | ETH_RXCTL |
| RGMII Receive Control | 7C | ETH_RST |
| Reset | 7B | ETH_MDC |
| Management Data Clock | 7B | ETH_MDIO |
| Management Data I/O | 7B | PHY_INT |
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Oscillators
Designator | Description | Frequency | Note |
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U2 | Ethernet | 25 MHz |
| U37 | FPGA | 50 MHz | Bank 5B and MAX10 | U35 | FPGA | 50 MHz | Bank 4A and 3B |
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| U44 | HPS | 25 MHz | CLK1, CLK2 | U32 | FTDI | 12 MHz |
| U3 | HDMI | 12 MHz |
| U34 | USB | 24 MHz |
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| HPS | 25 MHz | CLK1 HPS SOCKIT |
| HPS | 25 MHz | CLK2 HPS SOCKIT |
| FPGA | 50 MHz | Bank 3B SOCKIT |
| FPGA | 50 MHz | Bank 4A SOCKIT |
| FPGA | 50 MHz | Bank 5B SOCKIT |
| FPGA | 50 MHz | Bank 8A SOCKIT |
| FPGA | 50 MHz | Pin P8/9 SOCKIT |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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Power-On Sequence
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Voltage Monitor Circuit
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Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
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Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
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Disclaimer