Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

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    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
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        • "Table_RH_DCH" for Document_Change_History
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Note for Download Link of the Scroll ignore macro:

Download PDF version of this document.

Table of Contents


The Trenz Electronic CR00140-01 is a CRUVI motor driver module. It supports motors with up to 4 phases up to 40V.  

Refer to http://trenz.org/ for the current online version of this manual and other available documentation.

Notes :

Key Features

 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modues:

  • SoC/FPGA
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension

Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

  1. Motor connector screw terminal, J8
  2. Power supply screw terminal, J7
  3. 5x2 pinheader, base for TEI0004 JTAG programmer, J10
  4. 5x2 pinheader for sensor selection, J3
  5. 6x1 pinheader for single ended sensors, J1
  6. 5x2 pinheader for differential sensors, J2
  7. User push buttons, S1, S2
  8. User LEDs, D1, D2
  9. LED DC_Link, D4
  10. LED Power Good, D3
  11. DCDC for 15V, U1
  12. DCDC for 5V, U2
  13. half bridge drivers, U8, U9, U10, U11
  14. MAX10 CPLD, U25
  15. CRUVI high speed connector
  16. ADCs, U3, U5, U7
  17. Shunt resistors, R22, R28

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Storage device name



MAX10 CPLDdefault firmware REV01See firmware documentation

Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

CPLD BankB2B ConnectorI/O Signal CountVoltage LevelNotes
3J912 x LVDS / 24 I/OsVADJ6 x RX + 6 x TX
8J94 I/Os3.3VConstant 3.3V
1BJ95 I/Os3.3VJTAG, JTAGEN, Constant 3.3V

JTAG Interface

JTAG access to the CPLD of CR00140 is possible via the CRUVI high speed connector J9 and the pinheader J10, which is a base for TEI004 JTAG programmer. The JTAGEN signal is pulled up and available on J9 only. If JTAGEN is pulled low, the four signals can be used as user I/Os.

JTAG Signal

B2B Connector

Pin headerNotes
TMSJ9-55J10-5pull up
TDIJ9-51J10-9pull up


J10-1pull down
JTAGEN J9-57-high for enable JTAG port of CPLD, low for user I/Os, pull up
UART_RX-J10-7CPLD Firmware dependent, see Firmware
UART_TX-J10-8CPLD Firmware dependent, see Firmware
RST-J10-6CPLD Firmware dependent, see Firmware
+3.3V_DJ9-4, J9-9J10-4-
DGNDseveral, see CRUVIJ10-2, J10-10-

Sensor Interface

The pin headers J1, J2 and J3 constitute the sensor interface. It can be e.g. used with Encoders or Hall sensors. J3 is the selector between differential sensor interface (J2) or single ended sensors (J1). Connecting sensors is only allowed to one of the two pinheaders (J1/J2), the other one has to stay unconnected. In the figure below the jumper configuration of J3 to enable one or the other type of sensor interface is depicted.

The pinheaders for connection of the sensors are further described in the following table. For differential configuration 100 Ohm parallel termination is used.


 J1 pin (singel ended) J2 pin (differential)
+5.0V_D1, 62

Motor Interface

CR00140 has a motor interface, where up to 4 phases can be driven.

Check carefully correct connection of the phases of the motor, according to the motor and the implemented driving algorithm.


 J8 pin lableNote
Motor_AACurrent measurement via R22 and ADC U3
Motor_BBCurrent measurement via R28 and ADC U5


For the connection to a control unit, the CRUVI interface is implemented. One high speed connector J9 is assembled. The connectors are further described in section B2B Connectors. The connection of the signals and the voltage levels is described in the CPLD section.


 Connector - Pin

J9-12, J9-18, J9-24, J9-30, J9-42, J9-48, J9-54, J9-13, J9-19, J9-25, J9-31, J9-37, J9-43, J9-49


J9-4, J9-9





On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


A Intel/Altera MAX10 FPGA 10M08SAU169C8G (U25) is used as system controller. Table below lists the SC CPLD I/O signals and pins.

Signal nameSC CPLD PinCPLD BankConnected toFunctionNotes
A0_PJ83J9-14CPLD firmware dependentSee CPLD Firmware
A0_NK83J9-16CPLD firmware dependentSee CPLD Firmware


CPLD firmware dependentSee CPLD Firmware
A1_NM123J9-22CPLD firmware dependentSee CPLD Firmware
A2_PM93J9-26CPLD firmware dependentSee CPLD Firmware
A2_NM83J9-28CPLD firmware dependentSee CPLD Firmware
A3_PN83J9-32CPLD firmware dependentSee CPLD Firmware
A3_NN73J9-34CPLD firmware dependentSee CPLD Firmware
A4_PM73J9-38CPLD firmware dependentSee CPLD Firmware
A4_NN63J9-40CPLD firmware dependentSee CPLD Firmware
A5_PK53J9-44CPLD firmware dependentSee CPLD Firmware
A5_NJ53J9-46CPLD firmware dependentSee CPLD Firmware
B0_PN53J9-15CPLD firmware dependentSee CPLD Firmware
B0_NN43J9-17CPLD firmware dependentSee CPLD Firmware
B1_PJ73J9-21CPLD firmware dependentSee CPLD Firmware
B1_NK73J9-23CPLD firmware dependentSee CPLD Firmware
B2_PL113J9-27CPLD firmware dependentSee CPLD Firmware
B2_NM113J9-29CPLD firmware dependentSee CPLD Firmware
B3_PL103J9-33CPLD firmware dependentSee CPLD Firmware
B3_NM103J9-35CPLD firmware dependentSee CPLD Firmware
B4_PJ63J9-398CPLD firmware dependentSee CPLD Firmware
B4_NK63J9-41CPLD firmware dependentSee CPLD Firmware
B5_PL53J9-45CPLD firmware dependentSee CPLD Firmware
B5_NL43J9-47CPLD firmware dependentSee CPLD Firmware
HSION93J9-2CPLD firmware dependentSee CPLD Firmware
HSON103J9-6CPLD firmware dependentSee CPLD Firmware
RESETM53J9-8CPLD firmware dependentSee CPLD Firmware
HSIN123J9-10CPLD firmware dependentSee CPLD Firmware


F51BJ9-51, J10-9JTAG / user IO CPLD firmware dependentSee CPLD Firmware
TDOF61BJ9-53, J10-3JTAG / user IO CPLD firmware dependentSee CPLD Firmware
TMSG11BJ9-55, J10-5JTAG / user IO CPLD firmware dependentSee CPLD Firmware
JTAGENE51BJ9-57JTAG enable CPLD firmware dependentSee CPLD Firmware
TCKG21BJ9-59, J10-1JTAG / user IO CPLD firmware dependentSee CPLD Firmware
SMB_ALERTK22J9-3CPLD firmware dependentSee CPLD Firmware
SMB_SDAH52J9-5CPLD firmware dependentSee CPLD Firmware
SMB_SCLH42J9-7CPLD firmware dependentSee CPLD Firmware
REFCLKM22J9-11CPLD firmware dependentSee CPLD Firmware
BUTTON1C108S2CPLD firmware dependentactiv low, See CPLD Firmware 
BUTTON2B108S1CPLD firmware dependentactiv low, See CPLD Firmware 
ENC_AA108U13-13Sensor input channel A-
ENC_BA98U13-12Sensor input channel B-
ENC_IA118U13-14Sensor input channel I-
LED0D68D2CPLD firmware dependentSee CPLD Firmware
LED1B28D1CPLD firmware dependentSee CPLD Firmware
M_BEMF_B_DB58U15-13Back EMF signal phase B-
M_BEMF_C_DA58U15-12Back EMF signal phase C-


Back EMF signal phase A-
M_PWM_AHF11AU8-2Phase A half bridge high (DC_LINK) side driver signal-
M_PWM_ALE31AU8-3Phase A half bridge low (PGND) side driver signal-
M_PWM_BHE11AU9-2Phase B half bridge high (DC_LINK)side driver signal-
M_PWM_BLD11AU9-3Phase B half bridge low (PGND) side driver signal-
M_PWM_CHE41AU10-2Phase C half bridge high (DC_LINK)side driver signal-
M_PWM_CLC11AU10-3Phase C half bridge low (PGND) side driver signal-
M_PWM_DHC21AU11-2Phase D half bridge high (DC_LINK) side driver signal-
M_PWM_DLB11AU11-3Phase D half bridge low (PGND) side driver signal-
SD_IAE68U3-6Current measurement phase A33 Ohm series Resistor
SCLK_AB38U3-7, U5-7Clock for ADC for current measurement phase A and B(5-20 MHz)
SD_VB48U7-6Voltage measurement DC_LINK33 Ohm series Resistor
SD_IBA28U5-6Current measurement phase B33 Ohm series Resistor
SCLK_V_AA38U7-7Clock for ADC for voltage measurement DC_LINK(5-20 MHz)
M_DISABLE_D_DJ12U11-5Halfe bridge disable phase Ddisabled when high, pull up connected
M_DISABLE_A_DM12U8-5Halfe bridge disable phase Adisabled when high, pull up connected 
M_DISABLE_B_DL22U9-5Halfe bridge disable phase Bdisabled when high, pull up connected 
M_DISABLE_C_DK12U10-5Halfe bridge disable phase Cdisabled when high, pull up connected 
REFCLKM22J9-11CPLD firmware dependent-
RSTM32J10-6CPLD firmware dependent-
UART_RXN22J10-7CPLD firmware dependent-
UART_TXN32J10-8CPLD firmware dependent-
CLK_25MHZH62U26-3Clock input for accurate 25 Mhz clk.-

CPLD Bank Voltages


Schematic Name


1A+3.3V_D3.3VProvided via CRUVI


3.3VProvided via CRUVI
2+3.3V_D3.3VProvided via CRUVI
3VADJ1.8V, 2.5V, 3.3VProvided via CRUVI, supported voltage levels are determined by the CPLD Firmware, and the connected base/controller.

Provided via CRUVI


DesignatorColorConnected toSignal nameActive LevelNote
D1greenU25-B2LED1highUser LED, CPLD Firmware dependent, see Firmware description.
D2greenU25-D6LED0highUser LED, CPLD Firmware dependent, see Firmware description.
D3greenU1-A3, U2-B1PGOODhighON when +15.0V_M and +5.0V_M regulator indicated power good. Connected via transistor T1.
D4greenDC_LINK-lowON when DC_LINK above 11.7V. Connected via comparator U14D to DC_LINK


DesignatorConnected toSignal nameActive LevelNote
S1U25-B10BUTTON2lowUser button, CPLD Firmware dependent, see Firmware description.
S2U25-C10BUTTON1lowUser button, CPLD Firmware dependent, see Firmware description.


There are three isolating AD7403-8 ADCs for continous measurement oft phase A current (U3), phase B current (U5) and the DC_LINK voltage (U7) on board. The currents are measured through the shunt resistors R22, R28 for phase A and B respectively. The ADC clock is routed to the CPLD. For Currents the clock has the signal lable SCLK_A and for the voltage SCLK_V_A. The data signals are also routed to the CPLD. See CPLD Firmware for further description.


Back EMF zero crossing signals for sensor-less motor control are implemented for Phase A, B and C. They are routed via a triple channel Digital isolator (U15) to the CPLD. See CPLD Firmware for further description.

Half bridge drivers

Four ADuM7223 isolated half bridge drivers (U8, U9, U10, U11) are used for driving the four phases.


On the Motor side are two DCDCs on board. LTM8053 (U1) is utilized for the generation of the 15V transistor control voltage from VIN and can be measured on Testpoint TP1. A LTM8074 DCDC (U2) generates 5V from VIN for miscellaneous signals on the motor side of the PCB and can be measured on TP2.

Two isolated DCDCs ADUM5028 (U4, U6) are used for the generation two seperate clean 5V for the supply of the current measurement ADCs U3 and U5.

Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


The 2K Microchip 24AA02E48 EEPROM with pre-programmed unique 48bit address is connected to the CRUVI HS (Signals: SMB_SDA, SMB_SCL) connector and can e.g. be used for identifiction purposes.

Power Supply

The motor driving stage is supplied via connector J7 with maximum of 40V DC. Polarity of the powersupply is noted on the PCB.  

Check powersupply for correct polarity. Inversion of polarity will damage the module. At least Transistor T11 may be harmed. Furthermore make sure that under any circumstances the absolute maximum voltage does not exceed 42V.

Power Consumption

The power consumption on the motor stage side (J7) is dominated by the connected motor and the corresponding driving algorithm. The idle consumption is given below.

Power Input PinTypical CurrentNote
VIN~ 47mA@24V (J7), no motor connected, no PWM signal driven.

Power Distribution Dependencies

Power-On Sequence

There is no power on sequence which has to be maintained.

Power Rails

Power Rail Name

B2B Connectors



 J9-4, J9-9In-

Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

VINMotor supply voltage042V


digital part 3.3V supply voltage-0.33.9V
+5.0V_Ddigital part 5V supply voltage-0.36.0V
VADJIO Bank Voltage-0.33.9V

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN2240VLTM8053 datasheet


3.1353.465VMAX10 datasheet
+5.0V_D4.755.25VSN65LBC173AD datasheet

VADJ (3.3V operation)

VADJ (2.5V operation)

VADJ (1.8V operation)







VMAX10 datasheet
T-40105°CAD7403-8 (junction)
T (ambient)-4085°CSN65LBC173AD datasheet

Physical Dimensions

PCB thickness: 1.6 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Trenz shop CR00140 overview page
English pageGerman page

Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents


  • Date format:  YYYY-MM-DD

DateRevisionChangesDocumentation Link

removed LS connector J11,

added EEPROM U16


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


  • initial version



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