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Table of contents

Overview

CR00140 SC CPLD design for MAX10 with designator U25:  10M08SAU169C8G.

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History.

Product Specification

Port Description

VHDL Port nameDirectionSC CPLD PinCPLD BankConnected toFunctionNotes
A0_PinJ83J9-14PWM signal phase B, low-
A0_NinK83J9-16PWM signal phase D, high-
A1_PinM133

J9-20

PWM signal phase A, low-
A1_NinM123J9-22PWM signal phase C, high-
A2_PinM93J9-26PWM signal phase D, low-
A2_NinM83J9-28PWM signal phase C, low-
A3_PinN83J9-32PWM signal phase B, high-
A3_NinN73J9-34PWM signal phase A, high-
A4_PoutM73J9-38current measurement phase B-
A4_NoutN63J9-40push button S2 signal-
A5_PoutK53J9-44motor disable signaldisabled when high
A5_N
J53J9-46CPLD - CRUVI communicationcurrently not used
B0_P
N53J9-15CPLD - CRUVI communicationcurrently not used
B0_NinN43J9-17LED D2 signalactive high
B1_P
J73J9-21CPLD - CRUVI communicationPWM enable
B1_NinK73J9-23clock input for ADCs5-20 MHz
B2_PoutL113J9-27Encoder/Sensor signal A-
B2_NoutM113J9-29Encoder/Sensor signal B-
B3_PoutL103J9-33Encoder/Sensor signal I-
B3_NoutM103J9-35Back EMF signal phase B-
B4_PoutJ63J9-398Back EMF signal phase C-
B4_NoutK63J9-41Back EMF signal phase A-
B5_PoutL53J9-45current measurement phase A-
B5_NoutL43J9-47voltage measurement DC_LINK-
HSIO
N93J9-2CPLD - CRUVI I/O communicationcurrently not used
HSO
N103J9-6
RESET
M53J9-8
HSI
N123J9-10

TDI


F51BJ9-51, J10-9JTAG / user IO CPLD firmware dependentJTAG pinsharing currently not enabled
TDO
F61BJ9-53, J10-3JTAG / user IO CPLD firmware dependent
TMS
G11BJ9-55, J10-5JTAG / user IO CPLD firmware dependent
JTAGEN
E51BJ9-57JTAG enable CPLD firmware dependent
TCK
G21BJ9-59, J10-1JTAG / user IO CPLD firmware dependent
SMB_ALERT
K22J9-3CPLD - CRUVI I/O communicationcurrently not used
SMB_SDA
H52J9-5
SMB_SCL
H42J9-7
REFCLK
M22J9-11
BUTTON1inC108S2User button forwarded to CRUVIactiv low
BUTTON2inB108S1Motor control enable/disableactiv low
ENC_AinA108U13-13Sensor/Encoder input channel A-
ENC_BinA98U13-12Sensor/Encoder input channel B-
ENC_IinA118U13-14Sensor/Encoder input channel I-
LED0outD68D2User LED forwarded from CRUVIactive high
LED1outB28D1Status LED

blinking → motor control aktiv,

static on → system ok and motor control disabled

M_BEMF_B_DinB58U15-13Back EMF signal phase B-
M_BEMF_C_DinA58U15-12Back EMF signal phase C-
M_BEMF_A_DinA48

U15-14

Back EMF signal phase A-
M_PWM_AHoutF11AU8-2Phase A half bridge high (DC_LINK) side driver signal-
M_PWM_ALoutE31AU8-3Phase A half bridge low (PGND) side driver signal-
M_PWM_BHoutE11AU9-2Phase B half bridge high (DC_LINK)side driver signal-
M_PWM_BLoutD11AU9-3Phase B half bridge low (PGND) side driver signal-
M_PWM_CHoutE41AU10-2Phase C half bridge high (DC_LINK)side driver signal-
M_PWM_CLoutC11AU10-3Phase C half bridge low (PGND) side driver signal-
M_PWM_DHoutC21AU11-2Phase D half bridge high (DC_LINK) side driver signal-
M_PWM_DLoutB11AU11-3Phase D half bridge low (PGND) side driver signal-
SD_IAinE68U3-6Current measurement phase A-
SCLK_AoutB38U3-7, U5-7Clock for ADC for current measurement phase A and B(5-20 MHz)
SD_VinB48U7-6Voltage measurement DC_LINK-
SD_IBinA28U5-6Current measurement phase B-
SCLK_V_AoutA38U7-7Clock for ADC for voltage measurement DC_LINK(5-20 MHz)
M_DISABLE_D_DoutJ12U11-5Halfe bridge disable phase Ddisabled when high, pull up connected, weak pull up enabled
M_DISABLE_A_DoutM12U8-5Halfe bridge disable phase Adisabled when high, pull up connected, weak pull up enabled 
M_DISABLE_B_DoutL22U9-5Halfe bridge disable phase Bdisabled when high, pull up connected, weak pull up enabled 
M_DISABLE_C_DoutK12U10-5Halfe bridge disable phase Cdisabled when high, pull up connected, weak pull up enabled
REFCLK
M22J9-11-currently not used
RST
M32J10-6-currently not used (CPLD RESET)
UART_RX
N22J10-7-

currently not used/implemented (UART)
UART_TX
N32J10-8
CLK_25MHZinH62U26-3Clock input for accurate 25 Mhz.currently not used


Motor driver PWM signals

CRUVI interface signals are utilized to drive the half bridge PWM motor driver signals. They are logical connected to prevent driving the high and low simultanously:

M_PWM_AH <= '1' when ((A3_N='1') and (A1_P ='0')) else '0';
M_PWM_AL <= '1' when ((A1_P='1') and (A3_N ='0')) else '0';

M_PWM_BH <= '1' when ((A3_P='1') and (A0_P ='0')) else '0';
M_PWM_BL <= '1' when ((A0_P='1') and (A3_P ='0')) else '0';

M_PWM_CH <= '1' when ((A1_N='1') and (A2_N ='0')) else '0';
M_PWM_CL <= '1' when ((A2_N='1') and (A1_N ='0')) else '0';

M_PWM_DH <= '1' when ((A0_N='1') and (A2_P ='0')) else '0';
M_PWM_DL <= '1' when ((A2_P='1') and (A0_N ='0')) else '0';

Motor disable

The M_DISABLE signal set via push button S1 is used to disable all 4 motor drivers. This signal is logical or to the PWM enable signal from B1_P on the CRUVI connector.

M_DISABLE_OUT <= M_DISABLE or not B1_P;

M_DISABLE_A_D <= M_DISABLE_OUT;
M_DISABLE_B_D <= M_DISABLE_OUT;
M_DISABLE_C_D <= M_DISABLE_OUT;
M_DISABLE_D_D <= M_DISABLE_OUT;

The motor disable signal is also forwarded to the CRUVI interface:
A5_P <= M_DISABLE;

Sensor/Encoder, Back EMF

Sensor signals are forwarded to the CRUVI interface:

B2_P <= ENC_A;
B2_N <= ENC_B;
B3_P <= ENC_I;

B3_N <= M_BEMF_B_D;
B4_N <= M_BEMF_A_D;
B4_P <= M_BEMF_C_D;

Current and voltage measurement

Data signals from the 3 ADCs are forwarded to the CRUVI interface:
B5_N <= SD_V;
B5_P <= SD_IA;
A4_P <= SD_IB;

The corresponding clock signals are derived from the CRUVI interface signal B1_N:
SCLK_V_A <= B1_N;
SCLK_A <= B1_N;

Button

Motor disable button

S1 is utilized to switch the motor control on/off. The button is debounced. On press it switches the state of M_DISABLE signal and sets the corresponding LED status.

User Button

User button S2 is forwarded to the CRUVI interface signal A4_N:
A4_N <= BUTTON1;

LEDs

Status LED

The LED D1 is utilized for board status information in the following way:


Sequenz
Description
ONLED ONAll OK,  motor control disabled
********continuous blinkingAll OK,  motor control enabled
*ooooooo to *******o1 to 7 times blinking with a breakcurrently not used


USR LED

User LED D2 is controlled via the CRUVI signal B0_N:  
LED0 <= B0_N;

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

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Revision Changes

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV01REV01, REV02


initial version

All


Legal Notices