Template Revision 2.15

Template Change history:

  • 2.14 to 2.15
    • add excerpt macro to key features
  • 2.13 to 2.14
    • add fix table of content
    • add table size as macro
  • 2.12 to 2.13
    • Changed controller Signals section
  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.

Overview

The Trenz Electronic TE0835 is an extended-grade module based on Xilinx Zynq UltraScale+ RFSoC.  The module is equipped with 4x 8Gb DDR4 SDRAM Memory, 2x 512Mb SPI Flash Memory, USB2.0, Ethernet Transceiver and 2x Samtec Razor Beam Borard to Board (B2B) Connectors. The system controller CPLD is provided by Lattice MachXO2.

The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system. 

Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.


Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension



  • SoC/FPGA
    • Package: FFVE1156, FSVE1156
    • Device: ZU25, ZU27, ZU28, ZU43, ZU47, ZU48*
    • Engine: DR
    • Speed: -1, -L1, -2, -L2
    • Temperature: E, I*
  • RAM/Storage
    • 4x 8Gb DDR4 
    • 2x 512Mb SPI Flash
    • 2k I2C EEPROM
  • On Board
    • Lattice MachXO2  CPLD
    • Programmable Clock Generator
    • USB2.0 Transceiver
    • Gigabit Ethernet Transceiver
    • 3x Oscillators
    • 4x User LEDs
  • Interface
    • 2x Samtec Razor Beam ST5 (2x80 pol) Board to Board Connectors
  • Power
    • 5V Input Supply Voltage
  • Dimension
    • 90 x 65 mm
  • Note
    • * Different packages, speed and temperature range are available on assembly options

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .







Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Xilinx UltraScale+ RFSoC, U1
  2. 8Gb DDR4 SDRAM, U2,U3,U5,U9
  3. Voltage Regulators, U4,U6,U7
  4. User Red LEDs, D2...5
  5. Error/Status Red LEDs, D6...7
  6. Programmable Glock Generator, U15
  7. Lattice MachXO2 CPLD, U31
  8. Dual SPI Flash, U24-U25
  9. USB2.0 Transceiver, U11
  10. Pin Header 3x1, J3 (not Soldered)
  11. Green LED, D1
  12. Gigabit Ethernet Transceiver, U20
  13. EEPROM, U23
  14. B2B Connectors, J1
  15. B2B Connectors, J2

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

2x SPI Flash

Not Programmed


System Controller CPLDProgrammed
EEPROMNot Programmed
4x DDR4 SDRAMNot Programmed
Programmable Clock GeneratorNot Programmed


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

Configuration must be set through CPLD,U31 by setting MODE0...3 signals.

MODE[3:0]

Boot ModeNote

0000

PS_JTAG

Refer to CPLD Page
0001Quad SPI FlashRefer to CPLD Page
0101SD CardRefer to CPLD Page


The reset pin is active low.

Signal

B2BI/ONote

RESETN

J1-36InputPulled up to 3.3V_CPLD


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankB2B ConnectorNumber of I/OsVoltage Level Notes
Bank 500J112x Single Ended1.8VMIO14...25
Bank 501J120x Single Ended1.8VMIO26...51
Bank 505J118x Single Ended, 9x Differential pairs0.85VEXT_CLKIN_PSMGT, RX/TX0...3
Bank 128J1

2x Differnetial CLK Input,

8x Differential Transceiver

--B128_CLK, RX/TX0...3
Bank 129J1

2x Differnetial CLK Input

8x Differential Transceiver

--B129_CLK, RX/TX0...3
Bank 65J224x Single Ended, 12x Differential pairs1.8VHP Bank
Bank 88J216x Single Ended, 8x Differential pairs3.3VHD Bank
ADCJ2

16x Single Ended, 8x Differential pairs

4x Differential Clocks

Variable
DACJ2

16x Single Ended, 8x Differential pairs

3x Differential Clocks

Variable



JTAG Interface

JTAG access to the Xilinx UltraScale+ MPSoC is through B2B connector JM1. JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. When the CPLD_JTAGEN is 0 or off, it provides FPGA access and when it is 1 or ON, it provides CPLD access.

JTAG Signal

B2B Connector

JTAG_TMSJ1-24
JTAG_TDIJ1-20
JTAG_TDOJ1-18
JTAG_TCK

J1-22


MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



MIO PinConnected toB2BNotes
MIO0...12SPI FLash, U24-U25-Dual SPI FLash
MIO13LED Green, D1-3.3V_CPLD
MIO14...25FPGA Bank 500,U1J1PSMIO
MIO26...27FPGA Bank 501,U1J1PSMIO
MIO28...29CPLD, U31-

UART_TX, UART_RX

MIO30...31FPGA Bank 501, U1J1PSMIO
MIO32...33EEPROM,U23-I2C_SCL, I2C_SDA
MIO34...35FPGA Bank 501,U1J1PSMIO
MIO36Gigabit ETH, U20-ETH_RST
MIO37USB2.0, U11-USB_RST
MIO38...51FPGA Bank 501, U1J1PSMIO
MIO52...62USB2.0, U11-USB
MIO63...77Gigabit ETH, U20-ETH


Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Test PointSignalConnected toNotes
TP1CLKOUTVoltage Regulator, U7
TP2PLL_RSTNProgrammable Clock Generator, U15
TP4CPLD_JTAGEN

B2B, J1

CPLD, U31


TP5JTAG_TDO

B2B, J1

CPLD, U31


TP6JTAG_TDI

B2B, J1

CPLD, U31


TP7JTAG_TCK

B2B, J1

CPLD, U31


TP8JTAG_TMS

B2B, J1

CPLD, U31


TP9GNDGND
TP10...11

IO_L1P_AD15P_88, 

O_L4N_AD12N_88

FPGA Bank 88, U1
TP12VINB2B, J1
TP13...14GNDGND
TP15...16MIO32-MIO33

EEPROM,U23

FPGA Bank 501, U1


TP17GNDGND
TP18ADC_AVCCLDO Voltage Regulator, U8
TP19ADC_AVCCAUXLDO Voltage Regulator, U10
TP203.3V_CPLD

CPLD, U31

B2B, J1


T21CPLD_JT AGEN

B2B, J1

CPLD, U31




On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
QSPI FlashU24, U25
DDR4 SDRAMU2, U3, U5, U9
CPLDU31
USB2.0U11
Gigabit EthernetU20
Programmable Clock GeneratorU15
EEPROMU22
OscillatorsU14, U21, U12
LEDsD0...7


Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TE0835 is a Dual SPI Flash module equipped with two SPI Flash U24, U25 connecfted to PSMIO FPGA bank 500.

MIO PinSchematicU24 PinU25 PinNotes
MIO0MIO0_QSPICLK-
MIO1MIO1_QSPIDO-
MIO2MIO2_QSPInWP-
MIO3MIO3_QSPInHOLD-
MIO4MIO4_QSPIDI-
MIO5MIO5_QSPInCS-
MIO7MIO5_QSPI-nCS
MIO8MIO5_QSPI-DI
MIO9MIO5_QSPI-DO
MIO10MIO5_QSPI-nWP
MIO11MIO5_QSPI-nHOLD
MIO12MIO5_QSPI-CLK


System Controller CPLD

The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The  CPLD provides JTAG routing, boot mode, User IOs, LEDs, firmware and power management access. For more information please refer to the TE0835 CPLD page. 

Schematic/PinConnected toDescriptionNote
MODE0...3FPGA Bank 503, U1Boot Mode
POR_BFPGA Bank 503, U1Programming StatusPulled up
PORG_BFPGA Bank 503, U1Programming StatusPulled up
INIT_BFPGA Bank 503, U1Configuration initializationPulled up
DONEFPGA Bank 503, U1Configuration Done StatusPulled up
F_TCKFPGA Bank 503, U1FPGA JTAG
F_TDIFPGA Bank 503, U1FPGA JTAG
F_TMSFPGA Bank 503, U1FPGA JTAG
F_TDOFPGA Bank 503, U1FPGA JTAG
JTAG_TDOB2B, J1CPLD JTAG
JTAG_TMSB2B, J1CPLD JTAG
JTAG_TDIB2B, J1CPLD JTAG
JTAG_TCKB2B, J1CPLD JTAG
CPLD_JTAGENB2B, J1CPLD JTAG Enable
CPLDIO0...3B2B, J1CPLD IOs
RESETNB2B, J1Reset
MIO13LED Green, D13.3V_CPLD
MIO28FPGA Bank 501, U1UART_TX
MIO29FPGA Bank 501, U1UART_RX
FPGA_IO0...1FPGA Bank 65, U1IOs
EN_PS_PLVoltage Regulators, U6, U7, U29PS/PL Enable SignalsPulled Down
EN_GR1Voltage Regulators, U19, U27, U28MGTAVTT, PSLL Pulled Down
EN_GR2Voltage Regulators, U38, U18, U38PS_MGTRAVTT, 3.3, DDR2.5VPulled Down
EN_RF_ADCVoltage Regulators, U8Enable ADCPulled Down
PG_RF_DACVoltage Regulators, U17ADC Power Good Status Pulled Down
PG_PS_PLVoltage Regulators, U6, U7, U29PS/PL Power Good Status Pulled Down
EN_RF_DACVoltage Regulators, U13Enable DACPulled Down
PG_RF_DACVoltage Regulators, U10DAC Power Good Status Pulled Down


USB2.0

The TE0835 is equipped with a USB2.0, U11. 

U11 PinSchematicConnected toNotes
RESETBUSB0_RSTFPGA Bank 501, U1
VDDIO1.8V1.8V
CPENUSB0_CPEB2B, J1
VBUSUSB0_VBUSB2B, J1
IDUSB0_IDB2B, J1
DPUSB0_D_PB2B, J1
DMUSB0_D_NB2B, J1
REFCLKUSB_CLKOschillator, U12
STPUSB0_STPFPGA Bank 502, U1
NXTUSB0_NXTFPGA Bank 502, U1
DIRUSB0_DIRFPGA Bank 502, U1
CLKOUTUSB_CLKOschillator, U12
DATA0...7USB0_DATA0...8FPGA Bank 502, U1


Ethernet

The module TE0835 is equipped with a Gigabit Ethernet Transceiver, U20.

U20 PinSignal NameConnected toSignal DescriptionNote
MDIOETH_MDIOFPGA Bank 502, U1Data Management
MDCETH_MDCFPGA Bank 502, U1Data Management clock reference for the serial interface
TX_CLKETH_TXCKFPGA Bank 502, U1Transmit Clock
TX_CTRLETH_TXCTLFPGA Bank 502, U1Transmit Control
TXD0...3ETH_TXD0...3FPGA Bank 502, U1Transmit Data
RX_CLKETH_RXCKFPGA Bank 502, U1Receive Clock
RX_CTRLETH_RXCTLFPGA Bank 502, U1Receive Control
RXD0...3ETH_RXD0...3FPGA Bank 502, U1Receive Data
RESETnETH_RSTFPGA Bank 501, U1Ethernet reset, Active low.
XTAL_INETH_XTAL_INOscillator, U21Reference Clock

MDI0...3

PHY_MDI0...3B2B, J1Media Dependent Interface 0...3
LED0...1PHY_LED0...1B2B, J1LED output
LED/INTPHY_LED2B2B, J1LED interrupt


EEPROM

The module TE0835 has an EEPROM IC (U23) connected to PSMIO FPGA Bank 501.

MIO PinSchematicU23 PinNotes
MIO32MIO32_I2C1_SCLSCL
MIO33MIO33_I2C1_SDASDA



MIO PinI2C AddressDesignatorNotes
MIO32...330xA1U23


LEDs

DesignatorColorConnected toActive LevelNote
D1GreenMIO13Active High3.3V CPLD
D2...5RedDBG_LED0...3Active LowUser LED
D6RedERR_OUTActive High
D7RedERR_STATUSActive High


DDR4 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0835 SoM has 4x 1 Gigabyte volatile DDR4 SDRAM IC for storing user application code and data.

  • Part number: K4A8G165WB
  • Supply voltage: 1.2 V

  • Speed: 2400 Mbps

  • Temperature: -40 ~ 95 °C

Clock Sources

DesignatorDescriptionFrequencyNote
U14, U21MEMS Oscillator25MHz
U22MEMS Oscillator33.33 MHz
Y1Crystal Oscillator54 MHz
U12MEMS Oscillator52MHz
U15Programmable Clock GeneratorVariable


Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J3.  The I2C Address is 0x69.

U15 Pin
SignalConnected toDirectionNote

IN0

IN0_P

Oscillator, U14Input
IN1-N.C-
IN2EXT_CLK_IN1B2B,J2Input
IN3-N.C

nRST

PLL_RSTN

FPGA Bank 65,U1Input
SCLMIO32_I2C1_SCLPin Header, J3InputI2C
SDAMIO33_I2C1_SDAPin Header, J3InputI2C
OUT0

CLKC

B2B,J2Output

Differential Clock

OUT1CLKBB2B,J2OutputDifferential Clock
OUT2CLKAB2B,J2OutputDifferential Clock
OUT3CLKDB2B,J2OutputDifferential Clock
OUT4CLKEB2B,J2OutputDifferential Clock
OUT5CLKFB2B,J2OutputDifferential Clock
OUT6B128_CLK0FPGA Bank 128,U1Output
OUT7B129_CLK0FPGA Bank 129,U1Output
OUT8CLK8FPGA Bank 65,U1Output
OUT9PSMGT_100MHZFPGA Bank 505,U1Output
OUT9ACLK0A_100MHZB2B, J1Output


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VIN (5V)TBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence




Power Rails


Power Rail Name

B2B  J1 Pin

B2B  J2 Pin

DirectionNotes
VIN1,2,3,4,5,6,8-Input
PSBATT14-Input
3.3V_CPLD16-Output


Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 65 HPVCCO_651.8V
Bank 503 PSCONFIG

VCCO_PSIO3_503

1.8V
Bank 88 HDVCCO_883.3V
Bank 128 GTYMGTAVCC0.9V
Bank 129 GTYMGTAVCC0.9V
Bank 500 PSMIOVCCO_PSIO0_5001.8V
Bank 501 PSMIOVCCO_PSIO0_5011.8V
Bank 502VCCO_PSIO0_5021.8V
Bank 504 PSDDRVCCO_PSDDR_5041.2V
Bank 505 PSGTRPS_MGTRAVCC0.85V



Board to Board Connectors

  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage05V
T_STGStorage Temperature-4095°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN4.55.5VSee Schematic
T_OPR-4085°C

See USB2.0 Datasheet


Physical Dimensions

  • Module size: 90 mm × 65 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 7 mm.

PCB thickness: 1.65 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TE0835 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
2019-11-05REV01Initial ReleaseREV01
2020-06-17REV02

1. Added a VRP resistor on bank 65;

2. LDO U33 is changed on ADP7102ACPZ;

3. Signal FPGA IO0 is connected on AE18 pin of FPGA;

4. Signal DBG_LED3 is connected on AD18 pin of FPGA;

5. Signal MIO13_25 connected to J1 pin 33 instead MIO25.

6. Resistor R84 is removed;

7. LED D1 moved on edge of PCB;

8. Added THT testpoints J4 on CPLD_JTAGEN, R76 was removed;

9. Signals B49_XX_X are renamed in B88_XX_X;

10. C241 is changed on 1nF;

11. Length of CLK signals on RFADC and RFDAC are adjusted;

12. Wrong connection on U8 is fixed (PCB);

13. Wrong connection PGOOD1 pin of U7 is fixed;

14. R17 is changed from 35,5K to 33K for VCC_PL_PS correction.

REV02



Hardware revision number can be found on the PCB board together with the module model number separated by the dash.


|



Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • Bugfix Overview Picture
2021-12-21v.58John Hartfiel
  • Bugfix B2B section
  • Replace GTH with GTY
2021-05-28v.55John Hartfiel

  • Style update

  • Bugfix PDF Link
  • Key features update
2020-11-23v.51Pedram Babakhani
  • Update to REV02

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