Template Revision 2.15
Template Change history:
Important General Note:
Note for Download Link of the Scroll ignore macro:
The Trenz Electronic TE0835 is an extended-grade module based on Xilinx Zynq UltraScale+ RFSoC. The module is equipped with 4x 8Gb DDR4 SDRAM Memory, 2x 512Mb SPI Flash Memory, USB2.0, Ethernet Transceiver and 2x Samtec Razor Beam Borard to Board (B2B) Connectors. The system controller CPLD is provided by Lattice MachXO2.
The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system.
Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.
Key Features' must be split into 6 main groups for modules and mainboards:
Key Features' must be split into 6 main groups for carrier:
add drawIO object here.
Only components like EEPROM, QSPI flash can be initialized by default at manufacture.
If there is no components which might have initial data ( possible on carrier) you must keep the table empty
Configuration must be set through CPLD,U31 by setting MODE0...3 signals.
The reset pin is active low.
FPGA bank number and number of I/O signals connected to the B2B connector:
JTAG access to the Xilinx UltraScale+ MPSoC is through B2B connector JM1. JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. When the CPLD_JTAGEN is 0 or off, it provides FPGA access and when it is 1 or ON, it provides CPLD access.
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection
Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.
The TE0835 is a Dual SPI Flash module equipped with two SPI Flash U24, U25 connecfted to PSMIO FPGA bank 500.
The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The CPLD provides JTAG routing, boot mode, User IOs, LEDs, firmware and power management access. For more information please refer to the TE0835 CPLD page.
The TE0835 is equipped with a USB2.0, U11.
The module TE0835 is equipped with a Gigabit Ethernet Transceiver, U20.
The module TE0835 has an EEPROM IC (U23) connected to PSMIO FPGA Bank 501.
Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)
The TE0835 SoM has 4x 1 Gigabyte volatile DDR4 SDRAM IC for storing user application code and data.
Speed: 2400 Mbps
Temperature: -40 ~ 95 °C
There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J3. The I2C Address is 0x69.
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
Power supply with minimum current capability of 2.5A for system startup is recommended.
* TBD - To Be Determined
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 90 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 7 mm.
PCB thickness: 1.65 mm.
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
Set correct link to the shop page overview table of the product on English and German.
Example for TE0728:
For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:
Set correct links to download arrier, e.g. TE0706 REV02:
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.