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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

Overview

TEI0006 firmware for Intel MAX 10 FPGA U18: 10M08SAU169C8G

Feature Summary

• JTAG routing
• UART routing
• LED control
• Power control
• Reset
• Configuration mode selection

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

JTAG

JTAG signals are routed directly from B2B connector through Intel MAX 10 to Intel Cyclone 10 GX. Access between Intel MAX 10 and Intel Cyclone 10 GX can be multiplexed via JTAGEN. JTAGEN pin is already pulled up to 3.3V for access to Intel MAX 10, for access to Intel Cyclone 10 GX JTAGEN pin has to pulled down to GND on B2B connector J2-105.

With carrier board TEIB0006:

DIP Switch S1-1 position = OFF → access to Intel MAX 10

                                           ON → access to Intel Cyclone 10 GX

UART

UART signals are routed directly from B2B connector through Intel MAX 10 to Intel Cyclone 10 GX.

LED control

BASE_LED1 (B2B connector → J2-146) and the nCONFIG Pin from Intel Cyclone 10 GX are connected to user button BASE_BTN1 (B2B connector → J2-152).

BASE_LED2 (B2B connector → J2-148) is connected to user button BASE_BTN2 (B2B connector → J2-154).

LED1 is connected to nSTATUS pin from Intel Cyclone 10 GX.

LED2 is connected to GND.

LED3 and LED4 are connected to DATA0 pin from Intel Cyclone 10 GX.

Power control

EN_0V9 is set constant to logical one and enables power regulator U4 for 0.9V.

If power good signal PG_0V9 from power regulator U4 is set to logical one, output pin EN_0V95 is set to logical one and enables power regulator U7 for 0.95V.

If power good signal PG_0V95 from power regulator U4 is set to logical one, output pin EN_1V8 is set to logical one and enables power regulator U5 for 1.8V.

If power good signal PG_1V8 from power regulator U4 is set to logical one,

• output pin EN_1V8VIO is set to logical one and enables power regulator U6 for 1.8VIO,
• output pin EN_3V3MB is set to logical one  (connnected to J2-74 → enables power regulator U3 on carrier board TEIB0006),
• output pin EN_1V8MB is set to logical one (connected to J2-86 → enables power regulator U12 on carrier board TEIB0006),
• output pin EN_1V35 is set to logical one and enables power regulator U8 for 1.35V (VDD_DDR),
• output pin EN_VTT is set to logical one and enables power regulator U9 for VTT_DDR.

Reset

DEVCLRn (Device-wide reset) and clock reset PLL_RST for SI5345A are set constant to logical one.

Configuration mode selection

MSEL0 and MSEL1 are set constant to logical one. The selected configuration mode is "AS / Standard".

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices