Template Revision 1.8 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"


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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware


Table of contents

Intel MAX 10 Access

JTAGEN pin is already pulled up to 3.3V for access to Intel MAX 10.

With carrier board TEIB0006: Set DIP Switch S1-1 to OFF position.

For more Information see Firmware description TEI0006 Intel MAX 10 → JTAG.

Available Firmware

Description

Download

Firmware is available on:

General instructions

Firmware Update - General Requirements

Firmware Update - General Procedure

Important:

Procedure:

  1. Enable FPGA JTAG access (see JTAG section on Firmware description)
  2. Connect JTAG
  3. Power on system
  4. Open Quartus Prime
  5. Open Quartus Programmer from top menu: Tools → Programmer
  6. Select from Programmer top menu: Edit → Hardware Setup
  7. Select via the drop down menu: Arrow-USB-Blaster [USB0] (Installation of Arrow USB Programmer Driver needed) and close the window
  8. Click Add File...
  9. Select correct Firmware from Download area and press Open
  10. Click Start to program the device

More information are available on the Firmware description.