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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

Overview

TEI0006 firmware for Intel MAX 10 FPGA U18: 10M08SAU169C8G

Feature Summary

• JTAG routing
• UART routing
• LED control
• Power control
• Reset
• Configuration mode selection
• programming Oscillator SI5345A

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

JTAG

JTAG access to TEI0006 SoM only through B2B connector J2 available. The JTAG signals are routed directly from B2B connector through Intel MAX 10 to Intel Cyclone 10 GX.

Access between Intel MAX 10 and Intel Cyclone 10 GX can be selected via JTAGEN. JTAGEN pin is already pulled up to 3.3V for access to Intel MAX 10. For access to Intel Cyclone 10 GX JTAGEN pin has to pulled down to GND on B2B connector J2-105.

With carrier board TEIB0006:

DIP Switch S1-1 position = OFF → access to Intel MAX 10

                                           ON → access to Intel Cyclone 10 GX

UART

UART signals are routed directly from B2B connector through Intel MAX 10 to Intel Cyclone 10 GX.

LED control

BASE_LED1 (B2B connector → J2-146) and the NCONFIG Pin from Intel Cyclone 10 GX are connected to user button BASE_BTN1 (B2B connector → J2-152).

BASE_LED2 (B2B connector → J2-148) is connected to user button BASE_BTN2 (B2B connector → J2-154).

LED_FP_1 is connected to NSTATUS pin from Intel Cyclone 10 GX.

LED_FP_2 is connected to the fault status signal of the power sequencer core.

ON → no fault detected

OFF → fault detected

LED_FP_3 and LED_FP_4 are connected to DATA0 pin from Intel Cyclone 10 GX.

PHY1_LED1 is directly connected with PHY1_33LED1.

PHY1_LED2 is directly connected with PHY1_33LED2.

Power control

All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.

Output voltage VADJ of power regulator U11 is set to 1.8V via VADJ_VS0 pin, VADJ_VS1 pin and VADJ_VS2 pin (Pins are set to logical one).

Reset

DEVCLRN (Device-wide reset) pin for Intel Cyclone 10 GX and clock reset PLL_RST for the programmable Oscillator SI5345A are set to logical one.

Configuration mode selection

MSEL0 and MSEL1 are set to logical one. The selected configuration mode is "AS / Standard".

Programmable Oscillator SI5345A

The volatile memory of the programmable Oscillator SI5345A is configured via I2C interface with following clock frequencies.

Appx. A: Change History and Legal Notices

Revision Changes

• REV02 to REV03
  • add Power Sequencer Core
  • programm Oscillator SI5345A via I2C interface
• REV01 to REV02
  • add VADJ configuration for power regulator U11

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices