This step guides through the tasks which have to be done inside Intel Quartus Prime. As mentionend in page "Board bring-up overview for TEI0022", this step is for project generation, system setting and output creation. Therefore, the work within this step should be explained in three sections:
The section "Project Creation" describes the basic work to create a new project. The second section "System Setting" explains the creation of an HPS instance inside the project. And the third section "Output Creation" shows how to create the result output inside Intel Quartus Prime.
This section guides through the project creation:
Now, the following figure should be visible:
This section guides through the system setting with the Plattform Designer to generate and configure the HPS according to the physical board resources.
AXI Bridges:
FPGA-to-HPS interface width: Unused
HPS-to-FPGA interface width: Unused
Lightweight HPS-to-FPGA interface width: Unused
Subtab - Memory Parameters:
Memory device speed grade: 800.0 MHz
Total interface width: 32
Row Address width: 16
Column Address width: 10
Memory CAS latency setting: 5
ODT Rtt nominal value: RZQ/6
Memory write CAS latency settings: 5
Subtab - Board Settings:
Board Skews
Maximum CK delay to DIMM/device: 0.03
Maximum DQS delay to DIMM/device: 0.02
Minimum delay difference between CK and DQS: 0.09
Maximum delay difference between CK and DQS: 0.16
Maximum skew within DQS group: 0.01
Maximum skew between DQS groups: 0.08
Maximum skew within address and command bus: 0.03
Add connections via clicking into the circle marked with a red rectangle in the next figure:
hps_0 - h2f_reset → clk_0 - clk_in_reset
clk_0 - clk → hps_0 - f2h_sdram0_data
System → Assign Base Addresses
System → Assign Interrupt Numbers
System → Assign Custom Instruction Opcodes
System → Create Global Reset Network
Close the Plattform Designer by pressing Finish.
This section guides through the output creation:
Click onto the button with three dots (inside the red rectangle) in the opened window as visible in the next figure.
After this doing this guide, following files and folders are generated with the given purpose which are relevant for the next guide.
File/Folder | Purpose |
---|---|
.sopcinfo | SOPC Info File containing hardware description for the Device Tree Generator |
hps_isw_handoff | Folder containing a hardware description for the Preloader Generator |