Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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  max-width: 1200px !important;

Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment

    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


Note for Download Link of the Scroll ignore macro:

Download PDF version of this document.

Table of Contents


The Trenz Electronic TEI0023 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10.  Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to http://trenz.org/tei0023-info for the current online version of this manual and other available documentation.

Notes :

Key Features

 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination

Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

  1. SMA Connector, J5...6

  2. Amplifier, U12

  3. Voltage Reference, U8

  4. Analog to Digital Converter, U6

  5. Voltage Regulator, U4 - U10 - U13 - U16

  6. Switching Voltage Regulator, U11

  7. SDRAM Memory, U2

  8. Intel® MAX 10 FPGA, U1
  9. SPI Flash Memory, U5 (not populated)

  10. Oscillator, U7 - U19

  11. FTDI USB to JTAG/FIFO Adapter, U3

  12. User LEDs, D2...9

  13. FTDI Configuration EEPROM, U9

  14. Configuration/Status LED (Red) , D10

  15. Power-On LED (Green), D1

  16. Push Button, S1...2

  17. Micro USB Connector, J9

  18. 1x14 Pin Header, J2 (Not assembled)

  19. 1x6 Pin Header, J4 (Not assembled)

  20. 1x4 Pin Header, J3 (Not assembled)

  21. 1x14 Pin Header, J1 (Not assembled)

Initial Delivery State

Notes :

Only components like EEPROM, SPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Storage device name



Quad SPI Flash


Not populated


FTDI configuration

Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

FPGA Reconfigration can be triggered by pressing push button S1.


Push Button

Pin Header




J2Connected to nCONFIG

Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
Bank 8J213.3VRESET

FPGA I/O Banks

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.


MIO PinConnected toB2BNotes




FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2

112MHz Oscillator, U7CLK12M
41x14 Pin header, J1D2...5
3Amplifier, U12AMP_A0, AMP_A1, AMP_A2
1100MHz Oscillator, U19CLK_EN
Bank 59

1x14 Pin header, J2

21x14 Pin header, J1DIO0...1
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
Bank 8

8User Red LEDs, D2...9LED1...8
1Push Button, S2USER_BTN

Micro-USB Connector

The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232H chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.

PinsConnected toNote

FTDI FT2232H U3, DP pin


FTDI FT2232H U3, DM pin

JTAG Interface

JTAG access to the TEI0023 FPGA through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

JTAG Signal

Pin Header Connector



JTAG_ENJ4-2Pulled-up to 3.3V

Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.


Test PointSignalB2BNotes

Test PointSignalConnected toNotes
TP1+1.8 VV_Lin, U13   ↔   A2D, U12
TP2VREF_OUTV_Lin, U8   ↔   A2D, U6
TP6+14V_AV_Lin, U10   ↔   Amplifier, U12
TP7-14V_AV_Lin, U10   ↔   Amplifier, U12
TP8+14.5VV_Switch, U11 / D11   ↔   L6 / V_Lin u10
TP9-14.5VV_Switch, U11 / L12   ↔   L7 / V_Lin u10
TP10+5V5_Au16   ↔   V_Lin, U8 / A2D, U12

On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

SPI FlashU5
OscillatorU712 MHz clock source
ADCU12Analog to Digital Converter
Push ButtonsS1...2
8x User LEDsD2...9Red LEDs


TEI0023 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface.

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

Data input/output

DQ0 ... DQ15

bank 6

Data mask

DQM0 ... DQM1

bank 6

ClockCLKbank 3-
Control Signals


bank 3

Chip select


bank 3

Clock enable


bank 3

Row Address Strobe


bank 3

Column Address Strobe

WEbank 3Write Enable


The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4User configurable
BDBUS1BDBUS1FPGA bank 8, pin B4User configurable
BDBUS2BDBUS2FPGA bank 8, pin B5User configurable
BDBUS3BDBUS3FPGA bank 8, pin A6User configurable
BDBUS4BDBUS4FPGA bank 8, pin B6User configurable
BDBUS5BDBUS5FPGA bank 8, pin A7User configurable
BDBUS6BDBUS6FPGA bank 6, pin C11User configurable
BDBUS7BDBUS7FPGA bank 3, pin J7User configurable
BCBUS0BCBUS0FPGA bank 5, pin J9User configurable
BCBUS1BCBUS1FPGA bank 3, pin K5User configurable
BCBUS2BCBUS2FPGA bank 3, pin L4User configurable
BCBUS3BCBUS3FPGA bank 3, pin L5User configurable
BCBUS4BCBUS4FPGA bank 3, pin N12User configurable

SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

Signal Schematic NameConnected toNotes
F_CSFPGA bank 8, pin B3Chip select
F_CLKFPGA bank 8, pin A3Clock
F_DIFPGA bank 8, pin A2Data in / out

FPGA bank 8, pin C4

Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2Data in / out


The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

SchematicConnected toNotes




The TEI0023-XX-XXA board is equipped with the Analog Devices ADAQ4003BBCZ 18-bit 2MSPS ADC.

PinsConnected toNotes


Instrumentation Amplifier U14, VOUT-
IN-Instrumentation Amplifier U14, VOUT+
SDIFPGA, Bank 2, pin M2, ADC_SDI
SDOFPGA, Bank 2, pin M1,  ADC_SDO
SCKFPGA, Bank 2, pin N3,  ADC_SCK
CNVFPGA, Bank 2, pin N2, ADC_CNV


DesignatorColorConnected toActive LevelNote
D2...9RedLED1...8Active HighUser LEDs
D10RedCONF_DONEActive LowConfiguration DONE LED
D1Green3.3V Active HighAfter power on it will be on.

Push Bottuns

DesignatorConnected toFunctionalityNote
S1RESETGeneral reset
S2USER_BTNUser push buttonConnected to FPGA Bank 8.

Clock Sources

Clock SourceSchematic NameFrequencyNote
Microchip MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA Bank 2, pin H6.

Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of 1A for system startup is recommended.

Power Consumption

FPGATypical Current
Intel MAX 10 10M08 FPGA SoCTBD*

* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.

Power Rails

Power Rail Name


J2 Pin


J9 Pin

VINJ2-13-Input5 V - Pin Header


-J9-1Input5 V - USB Connector

Bank Voltages


Schematic Name


Bank 1AVCCIO1A3.3V
Bank 1B


Bank 2VCCIO23.3V
Bank 3VCCIO33.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V

Bank 8VCCIO83.3V

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnitReference Document


Supply voltage4.755.25V
CH1-, CH1+Analog input voltage on amplifier U12 pin 1, 10-2020VLTC6373 datasheet


Storage Temperature-65+125°C

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)-1010VLTC6373 datasheet



10M08SAU169C8G datasheet

Physical Dimensions

Module size: 25 mm × 86.5 mm.  Please download the assembly diagram for exact numbers.

PCB thickness: 1.598 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Trenz shop TE0728 overview page
English pageGerman page

Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents


  • Date format:  YYYY-MM-DD

DateRevisionChangesDocumentation Link
2020-02-0301Fill in TRM templateREV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


  • corrected link to Download area


v.41Antti Lukats
  • bugfix change history
2020-08-20v.36Antti Lukats
  • correction: Key features, overview, USB, SDRAM, SPI section
2020-02-04v.33ED, Kilian Jan
  • initial release



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