Template Revision 2.15

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

Template Change history:

  • 2.14 to 2.15
    • add excerpt macro to key features
  • 2.13 to 2.14
    • add fix table of content
    • add table size as macro
  • 2.12 to 2.13
    • Changed controller Signals section


Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download area of this document.

Overview

The Trenz Electronic TEB0835 is a carrier for TE0835 module which is based on Xilinx UltraScale+ RFSoC. The Carrier is equipped with a Micro SD card reader, Micro USB2.0, 21x UMCC connectors and 6x SMA connectors for clocks and ADC/DAC inputs/outputs , 6x Green User LEDs, Reset Push Button, DIP Switch for Mode, Battery Holder, FT2232H FTDI,  programmable clock generators and a Temperature sensor IC. The carrier provides PCIe connector as well.

Refer to http://trenz.org/teb0835-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension



  • Modules: 
    • TE0835
  • RAM/Storage
    • 4Kb EEPROM
  • On Board
    • Programmable Clock Generator
    • I2C Switch IC
    • 6x User Green LEDs
    • 16x RF Transformation
    • Reset Push Button
    • Temperature Sensor
    • FT2232H FTDI
    • SDIO Port Expander
    • 2x DIP Switch
    • Pin Headers
    • PCIe 6 Connector
  • Interface
    • 21x UMCC Connectors
    • 6x SMA Connectors
    • 2x Micro USB2.0
    • RJ45 LAN Socket
    • Micro SD Card Socket
    • 2x UEC5 Connectors
    • 2x UCC8 Connectors
    • PCIe x8 Card
    • 2x Samtec Razor Beam SS5 (2x80 pol) Board to Board Connectors
  • Power
    • 12V Input Supply Voltage
  • Dimension
    • 106.6  x 167.6 mm

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. SMA Connectors, J1,J3,J5,J7,J9,J11
  2. UMCC Connectors, J2,J4,J6,J8, J10, J12...16, J20, J27, J32...J38, J42...43
  3. Green LEDs, D6...11
  4. B2B Connector, J18
  5. B2B Connector, J17
  6. Micro SD Card Connector, J28
  7. Reset Push Button, BTN1
  8. PCIe 6 Pin Connector, J19
  9. Micro USB2.0 Connectors, J30
  10. Gigabit RJ45 Connector, J31
  11. DIP Switch, S1
  12. UEC5 Connector, J22,J24
  13. UCC8 Connector, J23,J25
  14. 1x4 Pin Header, J21
  15. FTDI, U12
  16. Green LEDs, D1...3
  17. 1x6 Pin Header, J40
  18. Micro USB2.0 Connectors (FTDI), J29
  19. PCIe-8x-kurz Card, J26
  20. Battery  Holder, B1
  21. DIP Switch (PLL SEL), S2
  22. Pin Header (PLL I2C), J41
  23. Jumper (PWR CFG), J39 
  24. EEPROM, U15
  25. RF Transformer, T2...17, T26...32
  26. Programmable Clock Generator, U5

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

EEPROMProgrammedFTDI Configuration


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

Push Button BTN1 is provided to switch OFF all power supplies on RFSoC board.

Signal

B2BI/ONote

RESETN

J17- 36InputConnected to Push Button, BTN1


There is a DIP switch S1 provided for enabling CPLD and set the FPGA boot mode. The DIP Switch setting should be set like the following table.

DIP

Signal

SettingNote
S1-A

CPLD_IO0

FPGA boot configBit 0, CPLD Firmware dependent.
S1-BCPLD_IO1FPGA boot configSDA pin
S1-CCPLD_IO2-PROGRAMN pin
S1-DCPLD_JTAGENCPLD JTAG ENJTAGENB


Boot Mode must be set using DIP Switch S1 on CPLD provided on the module TE0835. Please note that the DIP Switch is active low.

MODE Signal State

Boot Mode
S1-AS1-B
JTAGONON
QSPI FlashONOFF
SD CardOFFOFF


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

Number of I/O signals and interfaces connected to the B2B connectors:

B2B ConnectorInterfaceI/O Signal CountConnected toNotes
J17



I2C3x Single EndedI2C Switch, U7

PLL Intrupt

PLL Clocks

1x Single Ended

4x Single Ended, 2x Differential pairs

PLL Clock Generator, U5
JTAG4x Single EndedFTDI, U12

CPLD IO

CPLD Enable

3x Single Ended

1x Single Ended

DIP Switch, S1
PCIe Reset1x Single EndedPCIe Card, J26
UART2x Single EndedFTDI, U12

Ethernet LED

Ethernet MDI

2x Single Ended

8x Single Ended

RJ45  Connector, J31
SD Card6x Single Ended

Micro SD Memory Connector, J28

IO Expander,  U11


I/O16x Single Ended, 8x Differential pairsPCIe Card, J26PCIe
I/O16x Single Ended, 8x Differential pairsUEC5 Connector, J22UEC5
I/O16x Single Ended, 8x Differential pairsUEC5 Connector, J24UEC5
Micro USB2.0

2x Single Ended

1x Single Ended

2x Single Ended

Micro USB2.0 Connector, J30

Voltage Regulator, U17

Diode, D5


J18ADC16x Single Ended, 8x Differential pairs

SMA, J1, J3, J5, J7 

UMCC, J2, J4, J6, J8


ADC Clock4x Single Ended, 2x Differential pairsUMCC, J27, J32
DAC

16x Single Ended, 8x Differential pairs


SMA, J9, J11

UMCC, J10, J12, J13...16


DAC Clock4x Single Ended, 2x Differential pairsUMCC, J33, J34
Green LEDs6x Single Ended, 3x Differential pairsGreen LEDs, D6...11
I/O

10x Single Ended

UCC8 Connector, J23, J25UCC8


Gigabit Ethernet

Signal NameConnected toSignal DescriptionNote
PHY_MDI0...3B2B, J17Media Data
PHY_LED0...1B2B, J17Speed/Link Indicators LEDYellow/Green 


Micro USB for JTAG/UART

The TEB0835 is equipped with two Micro USB2.0 Connectors J29, J30. The Micro USB2.0 port, J29 is provided for JTAG/UART and it is connected to FTDI, U12.

DesignatorSignal NameConnected toNote
J29D_N/D_PFTDI,U12Data
USB_VBUSDiode, D4VBUS


Micro USB2.0

There is a Micro USB2.0 J30, provided for user.

DesignatorSignal NameConnected toNote
J30

USB_N/USB_PB2B, J17Data
USB0_VBUSB2B, J17VBUS
USB0_IDB2B, J17ID


Micro SD Card Reader

There is a Micro SD Card socket J28 connected to B2B J17 through an I/O expander U11.

PinSignal NameConnected toNote
VDD3.3V_SDB2B, J17connected to IO expander
CMDSD_CMDB2B, J17connected to IO expander
CLKSD_CLKB2B, J17connected to IO expander
DATA0...3SD_DATA0...3B2B, J17connected to IO expander
CDSD_CDB2B, J17


SMA Connectors

There are 6 SMA Connectors provided for Analog and Digital signals.

DesignatorSignal NameConnected toNote
J1ADC0_INB2B, J18Via RF Transformer T2
J3ADC2_INB2B, J18Via RF Transformer T6
J5ADC4_INB2B, J18Via RF Transformer T4
J7ADC6_INB2B, J18Via RF Transformer T8
J9DAC0_OUTB2B, J18Via RF Transformer T10
J11DAC2_OUTB2B, J18Via RF Transformer T12


UMCC Connectors

There are 21x UMCC Connectors provided for Analog /Digital signals and Clocks input and output.

DesignatorSignal NameConnected toNote
J2ADC1_INB2B, J18Via RF Transformer T3
J4ADC3_INB2B, J18Via RF Transformer T5
J6ADC5_INB2B, J18Via RF Transformer T7
J8ADC7_INB2B, J18Via RF Transformer T9
J10DAC1_OUTB2B, J18Via RF Transformer T11
J12DAC3_OUTB2B, J18Via RF Transformer T13
J13DAC4_OUTB2B, J18Via RF Transformer T14
J14DAC5_OUTB2B, J18Via RF Transformer T15
J15DAC6_OUTB2B, J18Via RF Transformer T16
J16DAC7_OUTB2B, J18Via RF Transformer T17
J27ADC_CLK_224B2B, J18Via RF Transformer T26
J20ADC_CLK_225B2B, J18Via RF Transformer T27
J32ADC_CLK_226B2B, J18Via RF Transformer T28
J33ADC_CLK_227B2B, J18Via RF Transformer T29
J34DAC_CLK_228B2B, J18Via RF Transformer T30
J35DAC_CLK_229B2B, J18Via RF Transformer T31
J36CLKIN1Programmable Clock Generator, U5
J37CLKIN2Programmable Clock Generator, U5
J38CLKOUT7Programmable Clock Generator, U5Via RF Transformer T32
J42CLKOUT8Programmable Clock Generator, U5
J43CLKOUT9Programmable Clock Generator, U5


UCE5 Connectors

The TEB0835 is equipped with two UCE5 Connectors.

DesignatorSignal NameConnected toNote
J22B128_TX0...3B2B, J178x Single Ended/ 4x LVDS Pairs
B128_RX0...3B2B, J178x Single Ended/ 4x LVDS Pairs
J24B129_TX0...3B2B, J178x Single Ended/ 4x LVDS Pairs
B129_RX0...3B2B, J178x Single Ended/ 4x LVDS Pairs


UCC8 Connectors

The TEB0835 is equipped with two UCC8 Connectors.

DesignatorSignal NameConnected toNote
J23FFA_MPRSB2B, J17
FFA_MSELB2B, J17
FFA_INTLB2B, J17
FFA_RSTLB2B, J17
FFA_SCL/FFA_SDAI2C Switch, U7
J25FFB_MPRSB2B, J17
FFB_MSELB2B, J17
FFB_INTLB2B, J17
FFB_RSTLB2B, J17
FFB_SCL/FFB_SDAI2C Switch, U7


PCIe 8x Short

There is a PICe-8x-Short card provided on the TEB0835 board.

Signal NameConnected toNote
B505_RX0...3B2B, J178x Single Ended/ 4x LVDS Pairs
B505_TX0...3B2B, J178x Single Ended/ 4x LVDS Pairs
EXT_CLKIN_PSMGTB2B, J17
PCIE_RSTB_RB2B, J17Pulled up to 1.8V


PCIe 6 Pins

PinSignal NameConnected toNote
112V_input_A

Regulator, U2







2
3
4GND

N.C




5
6


Pin Header 1x4

PinSignal NameConnected toNote
1GNDGND
2FAN_PWR12V
3FAN_TACHTepmerature Sensor, U9
4FAN_PWMTepmerature Sensor, U9


Pin Header 1x6

There is a 1x6 Pin Header J40, connected to JTAG signals as the following.

PinSignal NameConnected toNote
1JTAG_TMS

B2B, J17

FTDI, U12


2JTAG_TDI

B2B, J17

FTDI, U12


3JTAG_TDO

B2B, J17

FTDI, U12


4JTAG_TCK

B2B, J17

FTDI, U12


5GND-
63.3V_MODULEB2B, J17


Pin Header 1x3

There is a 1x3 Pin Header J41, it provides access to I2C signals which are connected to I2C Switch, U7.

PinSignal NameConnected toNote
1DSPLL0_SCL

I2C Switch, U7


2GND

I2C Switch, U7


3DSPLL0_SCL

I2C Switch, U7



Jumper

There is a Jumper J39 provided for setting the DCDC_EN between two signal level as the following. 

PinSignal NameConnected toNote
1PG_5VRegulator, U8
2DCDC_ENRegulator, U1, U4
3MODULE_PGB2B, J17


I2C Addresses

DesignatorI2C AddressNotes
U90x4CTemperature Sensor IC
U70x70I2C Switch
U50x68Programmable Clock Generator


Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Test PointSignalConnected toNotes
TP15VB2B, J17
TP2...3GNDGND
TP4ADC0_VCMB2B, J18
TP5ADC1_VCMB2B, J18
TP6USB_VBUSMicro USB2.0, J29
TP7UART0_RXB2B, J17
TP8UART0_TXB2B, J17
TP9ADC2_VCMB2B, J18
TP10ADC3_VCMB2B, J18
TP11ADC4_VCMB2B, J18
TP12ADC5_VCMB2B, J18
TP13ADC6_VCMB2B, J18
TP14ADC7_VCMB2B, J18
TP15PSBATTDiode, D13
TP16CLKE_P-
TP17CLKE_N-
TP18CLKF_P-
TP19CLKF_N-
TP20CLKD_P-
TP21CLKD_N-


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
EEPROMU15
FTDIU12
Temperature SensorU9
DIP SwitchS1, S2
Push ButtonBTN1
LEDsD1...11
OscillatorsU16, U6
PLL Clock  GeneratorU5



EEPROM

There is an EEPROM U15 provided in order to store the FTDI configuration.

PinSchematicConnected toNotes
CSEECSFTDI, U12
CLKEECLKFTDI, U12
DINEEDATAFTDI, U12


DIP Switch

There are two DIP Switches S1, S2 provided for boot mode and manual input select of programmable clock generator. For more information please refer to Configuration Signal Section

DesignatorPinSchematicConnected toNotes
S1S1ACPLD_IO0B2B, J17
S1BCPLD_IO1B2B, J17
S1CCPLD_IO2B2B, J17
S1DCPLD_JTAGENB2B, J17
S2S2ADSPLL0_SEL0Programmable clock Generator, U5
S2BDSPLL0_SEL0Programmable clock Generator, U5


Temperature Sensor

There is a temperature sensor IC U9 provided to capture the temperature and provides an alert when cooling is needed. the temperature IC is connected to I2C bus at address 0x4C.

PinSchematicConnected toNotes
TACHFAN_TACHPin Header, J21
PWMFAN_PWMPin Header, J21
D+DX_PRegulator, U8
D-DX_NRegulator, U8
nALERTALERT_N

I2C Switch, U7


nTCRITTHERM_Npulled up to 3.3V
SMBCLKI2C_SCL_SNSI2C Switch, U7
SMBDATI2C_SDA_SNSI2C Switch, U7


FTDI

The FTDI chip U12 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 2 I/O's of Channel B are routed to B2B J17 and must be used as UART.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U15.

FTDI PinSignal Schematic NameConnected toNotes
ADBUS0JTAG_TCK

B2B, J17

Pin Header, J40

JTAG interface
ADBUS1JTAG_TDI

B2B, J17

Pin Header, J40

ADBUS2JTAG_TDO

B2B, J17

Pin Header, J40

ADBUS3JTAG_TMS

B2B, J17

Pin Header, J40

BDBUS0UART0_RXB2B, J17UART
BDBUS1UART0_TXB2B, J17UART
EECS/EECLK/EEDATABDBUS2EEPROM, U15FTDI configuration
DM/DPD_N/D_PMicro USB2.0, J29FTDI Input


Push Button

DesignatorConnected toFunctionalityNote
BTN1RESETNGeneral Reset


LEDs

DesignatorColorConnected toActive LevelNote
D1GreenPG_1.8VHigh
D2GreenPG_3.3VHigh
D3GreenPG_5VHigh
D6...11GreenB2B, J18HighUser LED
D12GreenClock Generator, U5High


Clock Sources

DesignatorDescriptionFrequencyNote
U6MEMS Oscillator100 MHz
U16MEMS Oscillator12 MHz
Y1Crystal Oscillator54 MHz
U5Programmable Clock GeneratorVariable


Programmable Clock Generator

There is a programmable clock generator on-board (U5) provided in order to generate variable clocks for the module. The I2C Address is 0x68.

U5 Pin
SignalConnected toDirectionNote
IN0CLKIN0Oscillator, U6Input
IN1CLKIN1UMCC Connector, J36Input
IN2CLKIN2UMCC Connector, J37Input
IN3FBProgrammable Clock Generator, U5Input/Output
XA/XBCLK0_XA/XBOscillator, Y1Input
IN_SEL0...1DSPLL0_SEL0...1

I2C Switch, U7

DIP Switch, S2

Input
nINTRDSPLL0_INTR_NI2C Switch, U7Input
nLOLDSPLL0_LOL_NGreen LED, D12Input
nRSTDSPLL0_RST_N1.8 VInput
SCLKDSPLL0_SCLI2C Switch, U7Input
SDA/SDIODSPLL0_SDA

I2C Switch, U7

Pin Header, J41

In/Out
INTRPLL_INTR_NB2B, J17Output
OUT0ACLKOUT0AB2B, J17Output
OUT0CLKOUT0_PB2B, J17Output
OUT1PLLCLK1UMMC, J27Output
OUT2PLLCLK2UMMC, J20Output
OUT3PLLCLK3UMMC, J32Output
OUT4PLLCLK4UMMC, J33Output
OUT5PLLCLK5UMMC, J34Output
OUT6PLLCLK6UMMC, J35Output
OUT7CLKOUT7UMMC, J38Output
OUT8CLKOUT8UMMC, J42Output
OUT9CLKOUT9UMMC, J43Output
OUT9ACLKOUT9AProgrammable Clock Generator, U5Output


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence





Power Rails


Power Rail Name

B2B  JM17

B2B JM2

DirectionNotes
5V1,2,3,4,5,6,8-Ouput
PSBATT14-Output
3.3V_MODULE16-Input


Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage2.534V
ADC_VAnalog input voltage-5.05.0V
DAC_VDigital input voltage-5.05.0°C
T_STGStorage Temperature-55125°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN1113VSee the datasheet.
ADC_V05VSee the SMA datasheet
DAC_V05VSee the UMCC datasheet
T_OPT-40+85°CSee RF Transformer datasheet.


Physical Dimensions

  • Module size: 106.6 mm × 167.7 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

PCB thickness: 1.5 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TEB0835 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
2019-11-29REV01Initial ReleaseREV01
2020-08-13REV02
  1. All module's mount holes are connected to GND;
  2. CLK_Connectors. Added baluns for each clock inputs;
  3. Internal DSPLL is changed on SI5395A-A-GM;
  4. Added ability to use internal DSPLL as a source for each clock;
  5. Added clock inputs CLKIN1, CLKIN2 and clock outputs OUT1 , OUT2 connected to DSPLL.;
  6. All clock traces are matched with tolerance 0.2 mm;
  7. Lengths of inputs ADC0, ADC2, ADC4, ADC6 are matched with tolerance 0.2 mm;
  8. Lengths of outputs DAC0 and DAC2 are matched with tolerance 0.2 mm;
  9. Lengths of outputs DAC4, DAC5, DAC6, DAC7 are matched with tolerance 0.2 mm;
  10. In REV02: FTDI is powered from 3.3V_Module;
  11. Signal PLL_INTR_N is removed;
  12. Signal BOARD_PG is renamed in MODULE_PG;
  13. Added ability to select enable signal for internal DC-DCs 3.3V and 1.8V.
  14. Added JTAG connector J40.
  15. Added VBAT schematic. Added a holder for CR1220 3V battery
REV02



Hardware revision number can be found on the PCB board together with the module model number separated by the dash.





Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • update download link

2023-01-17v.54Kerstin Möller
  • Style update
2020-12-21v.51Pedram Babakhani
  • Update to 
    Revision 02

--

all

  • --


Disclaimer




Table of Contents